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target/riscv: Remove decode_RV32_64G()

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decodetree handles all instructions now so the fallback is not necessary
anymore.

Backports commit 25e6ca30c668783cd72ff97080ff44e141b99f9b from qemu
This commit is contained in:
Bastian Koppelmann 2019-03-19 05:37:40 -04:00 committed by Lioncash
parent a371684da9
commit e96282eb28
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 1 additions and 20 deletions
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21
qemu/target/riscv/translate.c
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@ -673,24 +673,6 @@ bool decode_insn16(DisasContext *ctx, uint16_t insn);
#include "decode_insn16.inc.c"
#include "insn_trans/trans_rvc.inc.c"
static void decode_RV32_64G(DisasContext *ctx)
{
uint32_t op;
/* We do not do misaligned address check here: the address should never be
* misaligned at this point. Instructions that set PC must do the check,
* since epc must be the address of the instruction that caused us to
* perform the misaligned instruction fetch */
op = MASK_OP_MAJOR(ctx->opcode);
switch (op) {
default:
gen_exception_illegal(ctx);
break;
}
}
static void decode_opc(DisasContext *ctx)
{
/* check for compressed insn */
@ -707,8 +689,7 @@ static void decode_opc(DisasContext *ctx)
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 4;
if (!decode_insn32(ctx, ctx->opcode)) {
/* fallback to old decoder */
decode_RV32_64G(ctx);
gen_exception_illegal(ctx);
}
}
}