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target/riscv: Convert to CPUClass::tlb_fill

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Note that env->pc is removed from the qemu_log as that value is garbage.
The PC isn't recovered until cpu_restore_state, called from
cpu_loop_exit_restore, called from riscv_raise_exception.

Backports commit 8a4ca3c10a96be6ed7f023b685b688c4d409bbcb from qemu
This commit is contained in:
Richard Henderson 2019-05-16 17:23:42 -04:00 committed by Lioncash
parent 14d48974a4
commit e98c731550
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
6 changed files with 29 additions and 33 deletions
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2
qemu/header_gen.py
View file

@ -5527,12 +5527,12 @@ riscv_symbols = (
'riscv_cpu_exec_interrupt',
'riscv_cpu_get_fflags',
'riscv_cpu_get_phys_page_debug',
'riscv_cpu_handle_mmu_fault',
'riscv_cpu_list',
'riscv_cpu_mmu_index',
'riscv_cpu_register_types',
'riscv_cpu_set_fflags',
'riscv_cpu_set_mode',
'riscv_cpu_tlb_fill',
'riscv_cpu_update_mip',
'riscv_csrrw',
'riscv_csrrw_debug',

2
qemu/riscv32.h
View file

@ -3444,12 +3444,12 @@
#define riscv_cpu_exec_interrupt riscv_cpu_exec_interrupt_riscv32
#define riscv_cpu_get_fflags riscv_cpu_get_fflags_riscv32
#define riscv_cpu_get_phys_page_debug riscv_cpu_get_phys_page_debug_riscv32
#define riscv_cpu_handle_mmu_fault riscv_cpu_handle_mmu_fault_riscv32
#define riscv_cpu_list riscv_cpu_list_riscv32
#define riscv_cpu_mmu_index riscv_cpu_mmu_index_riscv32
#define riscv_cpu_register_types riscv_cpu_register_types_riscv32
#define riscv_cpu_set_fflags riscv_cpu_set_fflags_riscv32
#define riscv_cpu_set_mode riscv_cpu_set_mode_riscv32
#define riscv_cpu_tlb_fill riscv_cpu_tlb_fill_riscv32
#define riscv_cpu_update_mip riscv_cpu_update_mip_riscv32
#define riscv_csrrw riscv_csrrw_riscv32
#define riscv_csrrw_debug riscv_csrrw_debug_riscv32

2
qemu/riscv64.h
View file

@ -3444,12 +3444,12 @@
#define riscv_cpu_exec_interrupt riscv_cpu_exec_interrupt_riscv64
#define riscv_cpu_get_fflags riscv_cpu_get_fflags_riscv64
#define riscv_cpu_get_phys_page_debug riscv_cpu_get_phys_page_debug_riscv64
#define riscv_cpu_handle_mmu_fault riscv_cpu_handle_mmu_fault_riscv64
#define riscv_cpu_list riscv_cpu_list_riscv64
#define riscv_cpu_mmu_index riscv_cpu_mmu_index_riscv64
#define riscv_cpu_register_types riscv_cpu_register_types_riscv64
#define riscv_cpu_set_fflags riscv_cpu_set_fflags_riscv64
#define riscv_cpu_set_mode riscv_cpu_set_mode_riscv64
#define riscv_cpu_tlb_fill riscv_cpu_tlb_fill_riscv64
#define riscv_cpu_update_mip riscv_cpu_update_mip_riscv64
#define riscv_csrrw riscv_csrrw_riscv64
#define riscv_csrrw_debug riscv_csrrw_debug_riscv64

5
qemu/target/riscv/cpu.c
View file

@ -344,14 +344,13 @@ static void riscv_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *da
//cc->gdb_num_core_regs = 65;
//cc->gdb_stop_before_watchpoint = true;
//cc->disas_set_info = riscv_cpu_disas_set_info;
#ifdef CONFIG_USER_ONLY
cc->handle_mmu_fault = riscv_cpu_handle_mmu_fault;
#else
#ifndef CONFIG_USER_ONLY
cc->do_unaligned_access = riscv_cpu_do_unaligned_access;
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
#endif
#ifdef CONFIG_TCG
cc->tcg_initialize = riscv_translate_init;
cc->tlb_fill = riscv_cpu_tlb_fill;
#endif
/* For now, mark unmigratable: */
//cc->vmsd = &vmstate_riscv_cpu;

5
qemu/target/riscv/cpu.h
View file

@ -266,8 +266,9 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type, int mmu_idx,
uintptr_t retaddr);
int riscv_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size,
int rw, int mmu_idx);
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
char *riscv_isa_string(RISCVCPU *cpu);
void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);

46
qemu/target/riscv/cpu_helper.c
View file

@ -380,53 +380,49 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
riscv_raise_exception(env, cs->exception_index, retaddr);
}
/* called by qemu's softmmu to fill the qemu tlb */
void tlb_fill(CPUState *cs, target_ulong addr, int size,
MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
{
int ret;
ret = riscv_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx);
if (ret == TRANSLATE_FAIL) {
RISCVCPU *cpu = RISCV_CPU(cs->uc, cs);
CPURISCVState *env = &cpu->env;
riscv_raise_exception(env, cs->exception_index, retaddr);
}
riscv_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr);
}
#endif
int riscv_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size,
int rw, int mmu_idx)
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
{
#ifndef CONFIG_USER_ONLY
RISCVCPU *cpu = RISCV_CPU(cs->uc, cs);
CPURISCVState *env = &cpu->env;
#if !defined(CONFIG_USER_ONLY)
hwaddr pa = 0;
int prot;
#endif
int ret = TRANSLATE_FAIL;
qemu_log_mask(CPU_LOG_MMU,
"%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx \
%d\n", __func__, env->pc, address, rw, mmu_idx);
qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
__func__, address, access_type, mmu_idx);
ret = get_physical_address(env, &pa, &prot, address, access_type, mmu_idx);
#if !defined(CONFIG_USER_ONLY)
ret = get_physical_address(env, &pa, &prot, address, rw, mmu_idx);
qemu_log_mask(CPU_LOG_MMU,
"%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
" prot %d\n", __func__, address, ret, pa, prot);
"%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
" prot %d\n", __func__, address, ret, pa, prot);
if (riscv_feature(env, RISCV_FEATURE_PMP) &&
!pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << rw)) {
!pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) {
ret = TRANSLATE_FAIL;
}
if (ret == TRANSLATE_SUCCESS) {
tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
prot, mmu_idx, TARGET_PAGE_SIZE);
} else if (ret == TRANSLATE_FAIL) {
raise_mmu_exception(env, address, rw);
return true;
} else if (probe) {
return false;
} else {
raise_mmu_exception(env, address, access_type);
riscv_raise_exception(env, cs->exception_index, retaddr);
}
#else
switch (rw) {
switch (access_type) {
case MMU_INST_FETCH:
cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
break;
@ -437,8 +433,8 @@ int riscv_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size,
cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
break;
}
cpu_loop_exit_restore(cs, retaddr);
#endif
return ret;
}
/*