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target/mips: Fix if-else-switch-case arms checkpatch errors in translate.c

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Remove if-else-switch-case-arms-related checkpatch errors.

Backports commit 1f8929d241c5461f3e98d52f54bcdadd35554448 from qemu
This commit is contained in:
Aleksandar Markovic 2019-06-30 19:42:14 -04:00 committed by Lioncash
parent 1e52cb8fa1
commit e9dc22c280
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 134 additions and 75 deletions
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191
qemu/target/mips/translate.c
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@ -2593,19 +2593,21 @@ static inline void gen_load_gpr(DisasContext *s, TCGv t, int reg)
{ {
TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv *cpu_gpr = tcg_ctx->cpu_gpr; TCGv *cpu_gpr = tcg_ctx->cpu_gpr;
if (reg == 0) if (reg == 0) {
tcg_gen_movi_tl(tcg_ctx, t, 0); tcg_gen_movi_tl(tcg_ctx, t, 0);
else } else {
tcg_gen_mov_tl(tcg_ctx, t, cpu_gpr[reg]); tcg_gen_mov_tl(tcg_ctx, t, cpu_gpr[reg]);
} }
}
static inline void gen_store_gpr(DisasContext *s, TCGv t, int reg) static inline void gen_store_gpr(DisasContext *s, TCGv t, int reg)
{ {
TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv *cpu_gpr = tcg_ctx->cpu_gpr; TCGv *cpu_gpr = tcg_ctx->cpu_gpr;
if (reg != 0) if (reg != 0) {
tcg_gen_mov_tl(tcg_ctx, cpu_gpr[reg], t); tcg_gen_mov_tl(tcg_ctx, cpu_gpr[reg], t);
} }
}
/* Moves to/from shadow registers. */ /* Moves to/from shadow registers. */
static inline void gen_load_srsgpr(DisasContext *s, int from, int to) static inline void gen_load_srsgpr(DisasContext *s, int from, int to)
@ -2613,9 +2615,9 @@ static inline void gen_load_srsgpr(DisasContext *s, int from, int to)
TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx); TCGv t0 = tcg_temp_new(tcg_ctx);
if (from == 0) if (from == 0) {
tcg_gen_movi_tl(tcg_ctx, t0, 0); tcg_gen_movi_tl(tcg_ctx, t0, 0);
else { } else {
TCGv_i32 t2 = tcg_temp_new_i32(tcg_ctx); TCGv_i32 t2 = tcg_temp_new_i32(tcg_ctx);
TCGv_ptr addr = tcg_temp_new_ptr(tcg_ctx); TCGv_ptr addr = tcg_temp_new_ptr(tcg_ctx);
@ -2835,11 +2837,12 @@ static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
static inline int get_fp_bit (int cc) static inline int get_fp_bit (int cc)
{ {
if (cc) if (cc) {
return 24 + cc; return 24 + cc;
else } else {
return 23; return 23;
} }
}
/* Addresses computation */ /* Addresses computation */
static inline void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, static inline void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0,
@ -2908,15 +2911,17 @@ static inline void gen_move_high32(DisasContext *s, TCGv ret, TCGv_i64 arg)
static inline void check_cp0_enabled(DisasContext *ctx) static inline void check_cp0_enabled(DisasContext *ctx)
{ {
if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) {
generate_exception_err(ctx, EXCP_CpU, 0); generate_exception_err(ctx, EXCP_CpU, 0);
} }
}
static inline void check_cp1_enabled(DisasContext *ctx) static inline void check_cp1_enabled(DisasContext *ctx)
{ {
if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) {
generate_exception_err(ctx, EXCP_CpU, 1); generate_exception_err(ctx, EXCP_CpU, 1);
} }
}
/* Verify that the processor is running with COP1X instructions enabled. /* Verify that the processor is running with COP1X instructions enabled.
This is associated with the nabla symbol in the MIPS32 and MIPS64 This is associated with the nabla symbol in the MIPS32 and MIPS64
@ -2924,18 +2929,20 @@ static inline void check_cp1_enabled(DisasContext *ctx)
static inline void check_cop1x(DisasContext *ctx) static inline void check_cop1x(DisasContext *ctx)
{ {
if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) {
generate_exception_end(ctx, EXCP_RI); generate_exception_end(ctx, EXCP_RI);
} }
}
/* Verify that the processor is running with 64-bit floating-point /* Verify that the processor is running with 64-bit floating-point
operations enabled. */ operations enabled. */
static inline void check_cp1_64bitmode(DisasContext *ctx) static inline void check_cp1_64bitmode(DisasContext *ctx)
{ {
if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) {
generate_exception_end(ctx, EXCP_RI); generate_exception_end(ctx, EXCP_RI);
} }
}
/* /*
* Verify if floating point register is valid; an operation is not defined * Verify if floating point register is valid; an operation is not defined
@ -2950,9 +2957,10 @@ static inline void check_cp1_64bitmode(DisasContext *ctx)
*/ */
static inline void check_cp1_registers(DisasContext *ctx, int regs) static inline void check_cp1_registers(DisasContext *ctx, int regs)
{ {
if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) {
generate_exception_end(ctx, EXCP_RI); generate_exception_end(ctx, EXCP_RI);
} }
}
/* Verify that the processor is running with DSP instructions enabled. /* Verify that the processor is running with DSP instructions enabled.
This is enabled by CP0 Status register MX(24) bit. This is enabled by CP0 Status register MX(24) bit.
@ -3040,9 +3048,10 @@ static inline void check_ps(DisasContext *ctx)
instructions are not enabled. */ instructions are not enabled. */
static inline void check_mips_64(DisasContext *ctx) static inline void check_mips_64(DisasContext *ctx)
{ {
if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) {
generate_exception_end(ctx, EXCP_RI); generate_exception_end(ctx, EXCP_RI);
} }
}
#endif #endif
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
@ -3127,13 +3136,12 @@ static inline void check_nms(DisasContext *ctx)
*/ */
static inline void check_nms_dl_il_sl_tl_l2c(DisasContext *ctx) static inline void check_nms_dl_il_sl_tl_l2c(DisasContext *ctx)
{ {
if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_NMS)) && if (unlikely((ctx->CP0_Config5 & (1 << CP0C5_NMS)) &&
!(ctx->CP0_Config1 & (1 << CP0C1_DL)) && !(ctx->CP0_Config1 & (1 << CP0C1_DL)) &&
!(ctx->CP0_Config1 & (1 << CP0C1_IL)) && !(ctx->CP0_Config1 & (1 << CP0C1_IL)) &&
!(ctx->CP0_Config2 & (1 << CP0C2_SL)) && !(ctx->CP0_Config2 & (1 << CP0C2_SL)) &&
!(ctx->CP0_Config2 & (1 << CP0C2_TL)) && !(ctx->CP0_Config2 & (1 << CP0C2_TL)) &&
!(ctx->CP0_Config5 & (1 << CP0C5_L2C))) !(ctx->CP0_Config5 & (1 << CP0C5_L2C)))) {
{
generate_exception_end(ctx, EXCP_RI); generate_exception_end(ctx, EXCP_RI);
} }
} }
@ -3182,23 +3190,56 @@ static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \
gen_ldcmp_fpr##bits (ctx, fp0, fs); \ gen_ldcmp_fpr##bits (ctx, fp0, fs); \
gen_ldcmp_fpr##bits (ctx, fp1, ft); \ gen_ldcmp_fpr##bits (ctx, fp1, ft); \
switch (n) { \ switch (n) { \
case 0: gen_helper_0e2i(tcg_ctx, cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc); break;\ case 0: \
case 1: gen_helper_0e2i(tcg_ctx, cmp ## type ## _ ## fmt ## _un, fp0, fp1, cc); break;\ gen_helper_0e2i(tcg_ctx, cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc); \
case 2: gen_helper_0e2i(tcg_ctx, cmp ## type ## _ ## fmt ## _eq, fp0, fp1, cc); break;\ break; \
case 3: gen_helper_0e2i(tcg_ctx, cmp ## type ## _ ## fmt ## _ueq, fp0, fp1, cc); break;\ case 1: \
case 4: gen_helper_0e2i(tcg_ctx, cmp ## type ## _ ## fmt ## _olt, fp0, fp1, cc); break;\ gen_helper_0e2i(tcg_ctx, cmp ## type ## _ ## fmt ## _un, fp0, fp1, cc); \
case 5: gen_helper_0e2i(tcg_ctx, cmp ## type ## _ ## fmt ## _ult, fp0, fp1, cc); break;\ break; \
case 6: gen_helper_0e2i(tcg_ctx, cmp ## type ## _ ## fmt ## _ole, fp0, fp1, cc); break;\ case 2: \
case 7: gen_helper_0e2i(tcg_ctx, cmp ## type ## _ ## fmt ## _ule, fp0, fp1, cc); break;\ gen_helper_0e2i(tcg_ctx, cmp ## type ## _ ## fmt ## _eq, fp0, fp1, cc); \
case 8: gen_helper_0e2i(tcg_ctx, cmp ## type ## _ ## fmt ## _sf, fp0, fp1, cc); break;\ break; \
case 9: gen_helper_0e2i(tcg_ctx, cmp ## type ## _ ## fmt ## _ngle, fp0, fp1, cc); break;\ case 3: \
case 10: gen_helper_0e2i(tcg_ctx, cmp ## type ## _ ## fmt ## _seq, fp0, fp1, cc); break;\ gen_helper_0e2i(tcg_ctx, cmp ## type ## _ ## fmt ## _ueq, fp0, fp1, cc); \
case 11: gen_helper_0e2i(tcg_ctx, cmp ## type ## _ ## fmt ## _ngl, fp0, fp1, cc); break;\ break; \
case 12: gen_helper_0e2i(tcg_ctx, cmp ## type ## _ ## fmt ## _lt, fp0, fp1, cc); break;\ case 4: \
case 13: gen_helper_0e2i(tcg_ctx, cmp ## type ## _ ## fmt ## _nge, fp0, fp1, cc); break;\ gen_helper_0e2i(tcg_ctx, cmp ## type ## _ ## fmt ## _olt, fp0, fp1, cc); \
case 14: gen_helper_0e2i(tcg_ctx, cmp ## type ## _ ## fmt ## _le, fp0, fp1, cc); break;\ break; \
case 15: gen_helper_0e2i(tcg_ctx, cmp ## type ## _ ## fmt ## _ngt, fp0, fp1, cc); break;\ case 5: \
default: abort(); \ gen_helper_0e2i(tcg_ctx, cmp ## type ## _ ## fmt ## _ult, fp0, fp1, cc); \
break; \
case 6: \
gen_helper_0e2i(tcg_ctx, cmp ## type ## _ ## fmt ## _ole, fp0, fp1, cc); \
break; \
case 7: \
gen_helper_0e2i(tcg_ctx, cmp ## type ## _ ## fmt ## _ule, fp0, fp1, cc); \
break; \
case 8: \
gen_helper_0e2i(tcg_ctx, cmp ## type ## _ ## fmt ## _sf, fp0, fp1, cc); \
break; \
case 9: \
gen_helper_0e2i(tcg_ctx, cmp ## type ## _ ## fmt ## _ngle, fp0, fp1, cc); \
break; \
case 10: \
gen_helper_0e2i(tcg_ctx, cmp ## type ## _ ## fmt ## _seq, fp0, fp1, cc); \
break; \
case 11: \
gen_helper_0e2i(tcg_ctx, cmp ## type ## _ ## fmt ## _ngl, fp0, fp1, cc); \
break; \
case 12: \
gen_helper_0e2i(tcg_ctx, cmp ## type ## _ ## fmt ## _lt, fp0, fp1, cc); \
break; \
case 13: \
gen_helper_0e2i(tcg_ctx, cmp ## type ## _ ## fmt ## _nge, fp0, fp1, cc); \
break; \
case 14: \
gen_helper_0e2i(tcg_ctx, cmp ## type ## _ ## fmt ## _le, fp0, fp1, cc); \
break; \
case 15: \
gen_helper_0e2i(tcg_ctx, cmp ## type ## _ ## fmt ## _ngt, fp0, fp1, cc); \
break; \
default: \
abort(); \
} \ } \
tcg_temp_free_i##bits (tcg_ctx, fp0); \ tcg_temp_free_i##bits (tcg_ctx, fp0); \
tcg_temp_free_i##bits (tcg_ctx, fp1); \ tcg_temp_free_i##bits (tcg_ctx, fp1); \
@ -3901,22 +3942,25 @@ static void gen_logic_imm(DisasContext *ctx, uint32_t opc,
uimm = (uint16_t)imm; uimm = (uint16_t)imm;
switch (opc) { switch (opc) {
case OPC_ANDI: case OPC_ANDI:
if (likely(rs != 0)) if (likely(rs != 0)) {
tcg_gen_andi_tl(tcg_ctx, cpu_gpr[rt], cpu_gpr[rs], uimm); tcg_gen_andi_tl(tcg_ctx, cpu_gpr[rt], cpu_gpr[rs], uimm);
else } else {
tcg_gen_movi_tl(tcg_ctx, cpu_gpr[rt], 0); tcg_gen_movi_tl(tcg_ctx, cpu_gpr[rt], 0);
}
break; break;
case OPC_ORI: case OPC_ORI:
if (rs != 0) if (rs != 0) {
tcg_gen_ori_tl(tcg_ctx, cpu_gpr[rt], cpu_gpr[rs], uimm); tcg_gen_ori_tl(tcg_ctx, cpu_gpr[rt], cpu_gpr[rs], uimm);
else } else {
tcg_gen_movi_tl(tcg_ctx, cpu_gpr[rt], uimm); tcg_gen_movi_tl(tcg_ctx, cpu_gpr[rt], uimm);
}
break; break;
case OPC_XORI: case OPC_XORI:
if (likely(rs != 0)) if (likely(rs != 0)) {
tcg_gen_xori_tl(tcg_ctx, cpu_gpr[rt], cpu_gpr[rs], uimm); tcg_gen_xori_tl(tcg_ctx, cpu_gpr[rt], cpu_gpr[rs], uimm);
else } else {
tcg_gen_movi_tl(tcg_ctx, cpu_gpr[rt], uimm); tcg_gen_movi_tl(tcg_ctx, cpu_gpr[rt], uimm);
}
break; break;
case OPC_LUI: case OPC_LUI:
if (rs != 0 && (ctx->insn_flags & ISA_MIPS32R6)) { if (rs != 0 && (ctx->insn_flags & ISA_MIPS32R6)) {
@ -6123,8 +6167,9 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
} }
out: out:
if (insn_bytes == 2) if (insn_bytes == 2) {
ctx->hflags |= MIPS_HFLAG_B16; ctx->hflags |= MIPS_HFLAG_B16;
}
tcg_temp_free(tcg_ctx, t0); tcg_temp_free(tcg_ctx, t0);
tcg_temp_free(tcg_ctx, t1); tcg_temp_free(tcg_ctx, t1);
} }
@ -6790,8 +6835,9 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
TCGContext *tcg_ctx = ctx->uc->tcg_ctx; TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
const char *register_name = "invalid"; const char *register_name = "invalid";
if (sel != 0) if (sel != 0) {
check_insn(ctx, ISA_MIPS32); check_insn(ctx, ISA_MIPS32);
}
switch (reg) { switch (reg) {
case CP0_REGISTER_00: case CP0_REGISTER_00:
@ -7540,8 +7586,9 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
TCGContext *tcg_ctx = ctx->uc->tcg_ctx; TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
const char *register_name = "invalid"; const char *register_name = "invalid";
if (sel != 0) if (sel != 0) {
check_insn(ctx, ISA_MIPS32); check_insn(ctx, ISA_MIPS32);
}
//if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { //if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
// gen_io_start(); // gen_io_start();
@ -8282,8 +8329,9 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
TCGContext *tcg_ctx = ctx->uc->tcg_ctx; TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
const char *register_name = "invalid"; const char *register_name = "invalid";
if (sel != 0) if (sel != 0) {
check_insn(ctx, ISA_MIPS64); check_insn(ctx, ISA_MIPS64);
}
switch (reg) { switch (reg) {
case CP0_REGISTER_00: case CP0_REGISTER_00:
@ -8987,8 +9035,9 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
TCGContext *tcg_ctx = ctx->uc->tcg_ctx; TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
const char *register_name = "invalid"; const char *register_name = "invalid";
if (sel != 0) if (sel != 0) {
check_insn(ctx, ISA_MIPS64); check_insn(ctx, ISA_MIPS64);
}
//if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { //if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
// gen_io_start(); // gen_io_start();
@ -9721,12 +9770,12 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 && if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) != ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=
(env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) {
tcg_gen_movi_tl(tcg_ctx, t0, -1); tcg_gen_movi_tl(tcg_ctx, t0, -1);
else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) > } else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
(env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) {
tcg_gen_movi_tl(tcg_ctx, t0, -1); tcg_gen_movi_tl(tcg_ctx, t0, -1);
else if (u == 0) { } else if (u == 0) {
switch (rt) { switch (rt) {
case 1: case 1:
switch (sel) { switch (sel) {
@ -9947,12 +9996,12 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
gen_load_gpr(ctx, t0, rt); gen_load_gpr(ctx, t0, rt);
if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 && if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) != ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=
(env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) {
/* NOP */ ; /* NOP */ ;
else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) > } else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
(env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) {
/* NOP */ ; /* NOP */ ;
else if (u == 0) { } else if (u == 0) {
switch (rd) { switch (rd) {
case 1: case 1:
switch (sel) { switch (sel) {
@ -10228,8 +10277,9 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
break; break;
case OPC_TLBWI: case OPC_TLBWI:
opn = "tlbwi"; opn = "tlbwi";
if (!env->tlb->helper_tlbwi) if (!env->tlb->helper_tlbwi) {
goto die; goto die;
}
gen_helper_tlbwi(tcg_ctx, tcg_ctx->cpu_env); gen_helper_tlbwi(tcg_ctx, tcg_ctx->cpu_env);
break; break;
case OPC_TLBINV: case OPC_TLBINV:
@ -10252,20 +10302,23 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
break; break;
case OPC_TLBWR: case OPC_TLBWR:
opn = "tlbwr"; opn = "tlbwr";
if (!env->tlb->helper_tlbwr) if (!env->tlb->helper_tlbwr) {
goto die; goto die;
}
gen_helper_tlbwr(tcg_ctx, tcg_ctx->cpu_env); gen_helper_tlbwr(tcg_ctx, tcg_ctx->cpu_env);
break; break;
case OPC_TLBP: case OPC_TLBP:
opn = "tlbp"; opn = "tlbp";
if (!env->tlb->helper_tlbp) if (!env->tlb->helper_tlbp) {
goto die; goto die;
}
gen_helper_tlbp(tcg_ctx, tcg_ctx->cpu_env); gen_helper_tlbp(tcg_ctx, tcg_ctx->cpu_env);
break; break;
case OPC_TLBR: case OPC_TLBR:
opn = "tlbr"; opn = "tlbr";
if (!env->tlb->helper_tlbr) if (!env->tlb->helper_tlbr) {
goto die; goto die;
}
gen_helper_tlbr(tcg_ctx, tcg_ctx->cpu_env); gen_helper_tlbr(tcg_ctx, tcg_ctx->cpu_env);
break; break;
case OPC_ERET: /* OPC_ERETNC */ case OPC_ERET: /* OPC_ERETNC */
@ -10340,8 +10393,9 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
goto out; goto out;
} }
if (cc != 0) if (cc != 0) {
check_insn(ctx, ISA_MIPS4 | ISA_MIPS32); check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
}
btarget = ctx->base.pc_next + 4 + offset; btarget = ctx->base.pc_next + 4 + offset;
@ -10799,10 +10853,11 @@ static void gen_movci(DisasContext *ctx, int rd, int rs, int cc, int tf)
return; return;
} }
if (tf) if (tf) {
cond = TCG_COND_EQ; cond = TCG_COND_EQ;
else } else {
cond = TCG_COND_NE; cond = TCG_COND_NE;
}
l1 = gen_new_label(tcg_ctx); l1 = gen_new_label(tcg_ctx);
t0 = tcg_temp_new_i32(tcg_ctx); t0 = tcg_temp_new_i32(tcg_ctx);
@ -10825,10 +10880,11 @@ static inline void gen_movcf_s(DisasContext *ctx, int fs, int fd, int cc,
TCGv_i32 t0 = tcg_temp_new_i32(tcg_ctx); TCGv_i32 t0 = tcg_temp_new_i32(tcg_ctx);
TCGLabel *l1 = gen_new_label(tcg_ctx); TCGLabel *l1 = gen_new_label(tcg_ctx);
if (tf) if (tf) {
cond = TCG_COND_EQ; cond = TCG_COND_EQ;
else } else {
cond = TCG_COND_NE; cond = TCG_COND_NE;
}
tcg_gen_andi_i32(tcg_ctx, t0, tcg_ctx->fpu_fcr31, 1 << get_fp_bit(cc)); tcg_gen_andi_i32(tcg_ctx, t0, tcg_ctx->fpu_fcr31, 1 << get_fp_bit(cc));
tcg_gen_brcondi_i32(tcg_ctx, cond, t0, 0, l1); tcg_gen_brcondi_i32(tcg_ctx, cond, t0, 0, l1);
@ -10847,10 +10903,11 @@ static inline void gen_movcf_d(DisasContext *ctx, int fs, int fd, int cc,
TCGv_i64 fp0; TCGv_i64 fp0;
TCGLabel *l1 = gen_new_label(tcg_ctx); TCGLabel *l1 = gen_new_label(tcg_ctx);
if (tf) if (tf) {
cond = TCG_COND_EQ; cond = TCG_COND_EQ;
else } else {
cond = TCG_COND_NE; cond = TCG_COND_NE;
}
tcg_gen_andi_i32(tcg_ctx, t0, tcg_ctx->fpu_fcr31, 1 << get_fp_bit(cc)); tcg_gen_andi_i32(tcg_ctx, t0, tcg_ctx->fpu_fcr31, 1 << get_fp_bit(cc));
tcg_gen_brcondi_i32(tcg_ctx, cond, t0, 0, l1); tcg_gen_brcondi_i32(tcg_ctx, cond, t0, 0, l1);
@ -10871,10 +10928,11 @@ static inline void gen_movcf_ps(DisasContext *ctx, int fs, int fd,
TCGLabel *l1 = gen_new_label(tcg_ctx); TCGLabel *l1 = gen_new_label(tcg_ctx);
TCGLabel *l2 = gen_new_label(tcg_ctx); TCGLabel *l2 = gen_new_label(tcg_ctx);
if (tf) if (tf) {
cond = TCG_COND_EQ; cond = TCG_COND_EQ;
else } else {
cond = TCG_COND_NE; cond = TCG_COND_NE;
}
tcg_gen_andi_i32(tcg_ctx, t0, tcg_ctx->fpu_fcr31, 1 << get_fp_bit(cc)); tcg_gen_andi_i32(tcg_ctx, t0, tcg_ctx->fpu_fcr31, 1 << get_fp_bit(cc));
tcg_gen_brcondi_i32(tcg_ctx, cond, t0, 0, l1); tcg_gen_brcondi_i32(tcg_ctx, cond, t0, 0, l1);
@ -12175,8 +12233,9 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
TCGLabel *l1 = gen_new_label(tcg_ctx); TCGLabel *l1 = gen_new_label(tcg_ctx);
TCGv_i64 fp0; TCGv_i64 fp0;
if (ft != 0) if (ft != 0) {
tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_NE, cpu_gpr[ft], 0, l1); tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_NE, cpu_gpr[ft], 0, l1);
}
fp0 = tcg_temp_new_i64(tcg_ctx); fp0 = tcg_temp_new_i64(tcg_ctx);
gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp0, fs);
gen_store_fpr64(ctx, fp0, fd); gen_store_fpr64(ctx, fp0, fd);