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target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT

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Emphasize that the is_jmp option exits to the main loop.

Backports commit 14407ec2007e18536ed34772eef46f6e0a0e3d0e from qemu
This commit is contained in:
Richard Henderson 2021-02-25 14:02:43 -05:00 committed by Lioncash
parent 2540911bdd
commit eaa6291aa7
4 changed files with 20 additions and 18 deletions
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8
qemu/target/arm/translate-a64.c
View file

@ -1802,7 +1802,7 @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
gen_helper_msr_i_daifclear(tcg_ctx, tcg_ctx->cpu_env, t1); gen_helper_msr_i_daifclear(tcg_ctx, tcg_ctx->cpu_env, t1);
tcg_temp_free_i32(tcg_ctx, t1); tcg_temp_free_i32(tcg_ctx, t1);
/* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */ /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
s->base.is_jmp = DISAS_UPDATE; s->base.is_jmp = DISAS_UPDATE_EXIT;
break; break;
default: default:
@ -1987,13 +1987,13 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
/* I/O operations must end the TB here (whether read or write) */ /* I/O operations must end the TB here (whether read or write) */
// Unicorn: commented out // Unicorn: commented out
//gen_io_end(); //gen_io_end();
s->base.is_jmp = DISAS_UPDATE; s->base.is_jmp = DISAS_UPDATE_EXIT;
} else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
/* We default to ending the TB on a coprocessor register write, /* We default to ending the TB on a coprocessor register write,
* but allow this to be suppressed by the register definition * but allow this to be suppressed by the register definition
* (usually only necessary to work around guest bugs). * (usually only necessary to work around guest bugs).
*/ */
s->base.is_jmp = DISAS_UPDATE; s->base.is_jmp = DISAS_UPDATE_EXIT;
} }
} }
@ -14620,7 +14620,7 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
gen_goto_tb(dc, 1, dc->base.pc_next); gen_goto_tb(dc, 1, dc->base.pc_next);
break; break;
default: default:
case DISAS_UPDATE: case DISAS_UPDATE_EXIT:
gen_a64_set_pc_im(dc, dc->base.pc_next); gen_a64_set_pc_im(dc, dc->base.pc_next);
/* fall through */ /* fall through */
case DISAS_EXIT: case DISAS_EXIT:

4
qemu/target/arm/translate-vfp.inc.c
View file

@ -125,7 +125,7 @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
* this to be the last insn in the TB). * this to be the last insn in the TB).
*/ */
if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
s->base.is_jmp = DISAS_UPDATE; s->base.is_jmp = DISAS_UPDATE_EXIT;
gen_io_start(tcg_ctx); gen_io_start(tcg_ctx);
} }
gen_helper_v7m_preserve_fp_state(tcg_ctx, tcg_ctx->cpu_env); gen_helper_v7m_preserve_fp_state(tcg_ctx, tcg_ctx->cpu_env);
@ -2909,6 +2909,6 @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
tcg_temp_free_i32(tcg_ctx, fptr); tcg_temp_free_i32(tcg_ctx, fptr);
/* End the TB, because we have updated FP control bits */ /* End the TB, because we have updated FP control bits */
s->base.is_jmp = DISAS_UPDATE; s->base.is_jmp = DISAS_UPDATE_EXIT;
return true; return true;
} }

12
qemu/target/arm/translate.c
View file

@ -2870,7 +2870,7 @@ static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn)
tcg_temp_free_i32(tcg_ctx, tcg_tgtmode); tcg_temp_free_i32(tcg_ctx, tcg_tgtmode);
tcg_temp_free_i32(tcg_ctx, tcg_regno); tcg_temp_free_i32(tcg_ctx, tcg_regno);
tcg_temp_free_i32(tcg_ctx, tcg_reg); tcg_temp_free_i32(tcg_ctx, tcg_reg);
s->base.is_jmp = DISAS_UPDATE; s->base.is_jmp = DISAS_UPDATE_EXIT;
} }
static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn) static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn)
@ -2893,7 +2893,7 @@ static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn)
tcg_temp_free_i32(tcg_ctx, tcg_tgtmode); tcg_temp_free_i32(tcg_ctx, tcg_tgtmode);
tcg_temp_free_i32(tcg_ctx, tcg_regno); tcg_temp_free_i32(tcg_ctx, tcg_regno);
store_reg(s, rn, tcg_reg); store_reg(s, rn, tcg_reg);
s->base.is_jmp = DISAS_UPDATE; s->base.is_jmp = DISAS_UPDATE_EXIT;
} }
/* Store value to PC as for an exception return (ie don't /* Store value to PC as for an exception return (ie don't
@ -5200,7 +5200,7 @@ static void gen_srs(DisasContext *s,
tcg_temp_free_i32(tcg_ctx, tmp); tcg_temp_free_i32(tcg_ctx, tmp);
} }
tcg_temp_free_i32(tcg_ctx, addr); tcg_temp_free_i32(tcg_ctx, addr);
s->base.is_jmp = DISAS_UPDATE; s->base.is_jmp = DISAS_UPDATE_EXIT;
} }
/* Generate a label used for skipping this instruction */ /* Generate a label used for skipping this instruction */
@ -8417,7 +8417,7 @@ static bool trans_SETEND(DisasContext *s, arg_SETEND *a)
} }
if (a->E != (s->be_data == MO_BE)) { if (a->E != (s->be_data == MO_BE)) {
gen_helper_setend(tcg_ctx, tcg_ctx->cpu_env); gen_helper_setend(tcg_ctx, tcg_ctx->cpu_env);
s->base.is_jmp = DISAS_UPDATE; s->base.is_jmp = DISAS_UPDATE_EXIT;
} }
return true; return true;
} }
@ -9164,7 +9164,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
break; break;
case DISAS_NEXT: case DISAS_NEXT:
case DISAS_TOO_MANY: case DISAS_TOO_MANY:
case DISAS_UPDATE: case DISAS_UPDATE_EXIT:
gen_set_pc_im(dc, dc->base.pc_next); gen_set_pc_im(dc, dc->base.pc_next);
/* fall through */ /* fall through */
default: default:
@ -9191,7 +9191,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
case DISAS_JUMP: case DISAS_JUMP:
gen_goto_ptr(dc); gen_goto_ptr(dc);
break; break;
case DISAS_UPDATE: case DISAS_UPDATE_EXIT:
gen_set_pc_im(dc, dc->base.pc_next); gen_set_pc_im(dc, dc->base.pc_next);
/* fall through */ /* fall through */
default: default:

14
qemu/target/arm/translate.h
View file

@ -151,7 +151,8 @@ static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
/* target-specific extra values for is_jmp */ /* target-specific extra values for is_jmp */
/* is_jmp field values */ /* is_jmp field values */
#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ /* CPU state was modified dynamically; exit to main loop for interrupts. */
#define DISAS_UPDATE_EXIT DISAS_TARGET_1
/* These instructions trap after executing, so the A32/T32 decoder must /* These instructions trap after executing, so the A32/T32 decoder must
* defer them until after the conditional execution state has been updated. * defer them until after the conditional execution state has been updated.
* WFI also needs special handling when single-stepping. * WFI also needs special handling when single-stepping.
@ -167,11 +168,12 @@ static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
* custom end-of-TB code) * custom end-of-TB code)
*/ */
#define DISAS_BX_EXCRET DISAS_TARGET_8 #define DISAS_BX_EXCRET DISAS_TARGET_8
/* For instructions which want an immediate exit to the main loop, /*
* as opposed to attempting to use lookup_and_goto_ptr. Unlike * For instructions which want an immediate exit to the main loop, as opposed
* DISAS_UPDATE this doesn't write the PC on exiting the translation * to attempting to use lookup_and_goto_ptr. Unlike DISAS_UPDATE_EXIT, this
* loop so you need to ensure something (gen_a64_set_pc_im or runtime * doesn't write the PC on exiting the translation loop so you need to ensure
* helper) has done so before we reach return from cpu_tb_exec. * something (gen_a64_set_pc_im or runtime helper) has done so before we reach
* return from cpu_tb_exec.
*/ */
#define DISAS_EXIT DISAS_TARGET_9 #define DISAS_EXIT DISAS_TARGET_9