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target/arm: Amend bad merge

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Lioncash 2019-11-28 03:16:53 -05:00
parent f2ec6bc22d
commit eadeae183d
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 21 additions and 17 deletions
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21
qemu/target/arm/translate-a64.c
View file

@ -483,7 +483,7 @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
void unallocated_encoding(DisasContext *s)
{
/* Unallocated and reserved encodings are uncategorized */
gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
}
@ -1302,8 +1302,8 @@ static inline bool fp_access_check(DisasContext *s)
return true;
}
gen_exception_insn(s, 4, EXCP_UDEF, syn_fp_access_trap(1, 0xe, false),
s->fp_excp_el);
gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
return false;
}
@ -1313,7 +1313,7 @@ static inline bool fp_access_check(DisasContext *s)
bool sve_access_check(DisasContext *s)
{
if (s->sve_excp_el) {
gen_exception_insn(s, 4, EXCP_UDEF, syn_sve_access_trap(),
gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_sve_access_trap(),
s->sve_excp_el);
return false;
}
@ -2066,8 +2066,8 @@ static void disas_exc(DisasContext *s, uint32_t insn)
switch (op2_ll) {
case 1: /* SVC */
gen_ss_advance(s);
gen_exception_insn(s, 0, EXCP_SWI, syn_aa64_svc(imm16),
default_exception_el(s));
gen_exception_insn(s, s->base.pc_next, EXCP_SWI,
syn_aa64_svc(imm16), default_exception_el(s));
break;
case 2: /* HVC */
if (s->current_el == 0) {
@ -2080,7 +2080,8 @@ static void disas_exc(DisasContext *s, uint32_t insn)
gen_a64_set_pc_im(s, s->pc_curr);
gen_helper_pre_hvc(tcg_ctx, tcg_ctx->cpu_env);
gen_ss_advance(s);
gen_exception_insn(s, 0, EXCP_HVC, syn_aa64_hvc(imm16), 2);
gen_exception_insn(s, s->base.pc_next, EXCP_HVC,
syn_aa64_hvc(imm16), 2);
break;
case 3: /* SMC */
if (s->current_el == 0) {
@ -2092,7 +2093,8 @@ static void disas_exc(DisasContext *s, uint32_t insn)
gen_helper_pre_smc(tcg_ctx, tcg_ctx->cpu_env, tmp);
tcg_temp_free_i32(tcg_ctx, tmp);
gen_ss_advance(s);
gen_exception_insn(s, 0, EXCP_SMC, syn_aa64_smc(imm16), 3);
gen_exception_insn(s, s->base.pc_next, EXCP_SMC,
syn_aa64_smc(imm16), 3);
break;
default:
unallocated_encoding(s);
@ -14409,7 +14411,8 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
if (s->btype != 0
&& s->guarded_page
&& !btype_destination_ok(insn, s->bt, s->btype)) {
gen_exception_insn(s, 4, EXCP_UDEF, syn_btitrap(s->btype),
gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
syn_btitrap(s->btype),
default_exception_el(s));
return;
}

17
qemu/target/arm/translate.c
View file

@ -3052,7 +3052,8 @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
undef:
/* If we get here then some access check did not pass */
gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), exc_target);
gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
syn_uncategorized(), exc_target);
return false;
}
@ -3415,7 +3416,7 @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
* for attempts to execute invalid vfp/neon encodings with FP disabled.
*/
if (s->fp_excp_el) {
gen_exception_insn(s, 4, EXCP_UDEF,
gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
return 0;
}
@ -4700,7 +4701,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
* for attempts to execute invalid vfp/neon encodings with FP disabled.
*/
if (s->fp_excp_el) {
gen_exception_insn(s, 4, EXCP_UDEF,
gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
return 0;
}
@ -6827,7 +6828,7 @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
}
if (s->fp_excp_el) {
gen_exception_insn(s, 4, EXCP_UDEF,
gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
return 0;
}
@ -6951,7 +6952,7 @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
off_rm = vfp_reg_offset(0, rm);
}
if (s->fp_excp_el) {
gen_exception_insn(s, 4, EXCP_UDEF,
gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
return 0;
}
@ -7446,7 +7447,7 @@ static void gen_srs(DisasContext *s,
* For the UNPREDICTABLE cases we choose to UNDEF.
*/
if (s->current_el == 1 && !s->ns && mode == ARM_CPU_MODE_MON) {
gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), 3);
gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), 3);
return;
}
@ -10816,7 +10817,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
* UsageFault exception.
*/
if (arm_dc_feature(s, ARM_FEATURE_M)) {
gen_exception_insn(s, 4, EXCP_INVSTATE, syn_uncategorized(),
gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
default_exception_el(s));
return;
}
@ -11066,7 +11067,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
}
/* All other insns: NOCP */
gen_exception_insn(s, 4, EXCP_NOCP, syn_uncategorized(),
gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized(),
default_exception_el(s));
break;
}