mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2025-07-09 20:07:23 +00:00
tcg: Merge opcode arguments into TCGOp
Rather than have a separate buffer of 10*max_ops entries, give each opcode 10 entries. The result is actually a bit smaller and should have slightly more cache locality. Backports commit 75e8b9b7aa0b95a761b9add7e2f09248b101a392 from qemu
This commit is contained in:
Richard Henderson
Lioncash
parent
7dd4afd8d9
commit
eb488f5bd6
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@ -77,10 +77,13 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
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* full translation cache
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*/
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if (!cpu->uc->block_full && HOOK_EXISTS_BOUNDED(cpu->uc, UC_HOOK_BLOCK, db->pc_first)) {
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// Unicorn: FIXME: Needs to be adjusted to work with new TCG
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#if 0
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// Save block address to see if we need to patch block size later
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cpu->uc->block_addr = db->pc_first;
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cpu->uc->size_arg = tcg_ctx->gen_op_buf[tcg_ctx->gen_op_buf[0].prev].args;
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gen_uc_tracecode(tcg_ctx, 0xf8f8f8f8, UC_HOOK_BLOCK_IDX, cpu->uc, db->pc_first);
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#endif
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} else {
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cpu->uc->size_arg = -1;
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}
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@ -5070,7 +5070,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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TCGv cpu_T1 = tcg_ctx->cpu_T1;
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TCGv *cpu_regs = tcg_ctx->cpu_regs;
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TCGv *cpu_seg_base = tcg_ctx->cpu_seg_base;
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TCGArg* save_opparam_ptr = tcg_ctx->gen_opparam_buf + tcg_ctx->gen_op_buf[tcg_ctx->gen_op_buf[0].prev].args;
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//TCGArg* save_opparam_ptr = tcg_ctx->gen_opparam_buf + tcg_ctx->gen_op_buf[tcg_ctx->gen_op_buf[0].prev].args;
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bool cc_op_dirty = s->cc_op_dirty;
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bool changed_cc_op = false;
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@ -9072,6 +9072,8 @@ case 0x101:
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goto unknown_op;
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}
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// FIXME: Amend this non-conforming garbage
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#if 0
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// Unicorn: patch the callback for the instruction size
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if (HOOK_EXISTS_BOUNDED(env->uc, UC_HOOK_CODE, pc_start)) {
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// int i;
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@ -9093,6 +9095,7 @@ case 0x101:
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*(save_opparam_ptr + 1) = s->pc - pc_start;
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}
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}
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#endif
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return s->pc;
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illegal_op:
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@ -20497,7 +20497,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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// Unicorn: save param buffer
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if (HOOK_EXISTS(env->uc, UC_HOOK_CODE)) {
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save_opparam_idx = tcg_ctx->gen_next_parm_idx;
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save_opparam_idx = tcg_ctx->gen_next_op_idx;
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}
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is_slot = ctx.hflags & MIPS_HFLAG_BMASK;
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@ -20525,7 +20525,8 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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printf("[%u] = %x\n", i, *(save_opparam_ptr + i));
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printf("\n");
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*/
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tcg_ctx->gen_opparam_buf[save_opparam_idx + insn_patch_offset] = insn_bytes;
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// FIXME
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//tcg_ctx->gen_op_buf[save_opparam_idx + insn_patch_offset] = insn_bytes;
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}
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}
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@ -587,7 +587,7 @@ void tcg_optimize(TCGContext *s)
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TCGArg tmp;
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TCGOp * const op = &s->gen_op_buf[oi];
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TCGArg * const args = &s->gen_opparam_buf[op->args];
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TCGArg * const args = op->args;
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TCGOpcode opc = op->opc;
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const TCGOpDef *def = &s->tcg_op_defs[opc];
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@ -1195,7 +1195,7 @@ void tcg_optimize(TCGContext *s)
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uint64_t b = ((uint64_t)bh << 32) | bl;
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TCGArg rl, rh;
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TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_movi_i32, 2);
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TCGArg *args2 = &s->gen_opparam_buf[op2->args];
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TCGArg *args2 = op2->args;
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if (opc == INDEX_op_add2_i32) {
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a += b;
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@ -1221,7 +1221,7 @@ void tcg_optimize(TCGContext *s)
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uint64_t r = (uint64_t)a * b;
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TCGArg rl, rh;
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TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_movi_i32, 2);
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TCGArg *args2 = &s->gen_opparam_buf[op2->args];
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TCGArg *args2 = op2->args;
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rl = args[0];
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rh = args[1];
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@ -44,108 +44,78 @@ extern TCGv_i32 TCGV_HIGH_link_error(TCGv_i64);
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Up to and including filling in the forward link immediately. We'll do
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proper termination of the end of the list after we finish translation. */
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static void tcg_emit_op(TCGContext *ctx, TCGOpcode opc, int args)
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static inline TCGOp *tcg_emit_op(TCGContext *ctx, TCGOpcode opc)
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{
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int oi = ctx->gen_next_op_idx;
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int ni = oi + 1;
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int pi = oi - 1;
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TCGOp op = {0};
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TCGOp *op = &ctx->gen_op_buf[oi];
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tcg_debug_assert(oi < OPC_BUF_SIZE);
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ctx->gen_op_buf[0].prev = oi;
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ctx->gen_next_op_idx = ni;
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op.opc = opc;
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op.args = args;
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op.prev = pi;
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op.next = ni;
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memset(op, 0, offsetof(TCGOp, args));
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op->opc = opc;
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op->prev = pi;
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op->next = ni;
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ctx->gen_op_buf[oi] = op;
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return op;
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}
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void tcg_gen_op1(TCGContext *ctx, TCGOpcode opc, TCGArg a1)
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{
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int pi = ctx->gen_next_parm_idx;
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tcg_debug_assert(pi + 1 <= OPPARAM_BUF_SIZE);
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ctx->gen_next_parm_idx = pi + 1;
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ctx->gen_opparam_buf[pi] = a1;
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tcg_emit_op(ctx, opc, pi);
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TCGOp *op = tcg_emit_op(ctx, opc);
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op->args[0] = a1;
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}
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void tcg_gen_op2(TCGContext *ctx, TCGOpcode opc, TCGArg a1, TCGArg a2)
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{
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int pi = ctx->gen_next_parm_idx;
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tcg_debug_assert(pi + 2 <= OPPARAM_BUF_SIZE);
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ctx->gen_next_parm_idx = pi + 2;
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ctx->gen_opparam_buf[pi + 0] = a1;
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ctx->gen_opparam_buf[pi + 1] = a2;
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tcg_emit_op(ctx, opc, pi);
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TCGOp *op = tcg_emit_op(ctx, opc);
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op->args[0] = a1;
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op->args[1] = a2;
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}
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void tcg_gen_op3(TCGContext *ctx, TCGOpcode opc, TCGArg a1,
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TCGArg a2, TCGArg a3)
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{
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int pi = ctx->gen_next_parm_idx;
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tcg_debug_assert(pi + 3 <= OPPARAM_BUF_SIZE);
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ctx->gen_next_parm_idx = pi + 3;
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ctx->gen_opparam_buf[pi + 0] = a1;
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ctx->gen_opparam_buf[pi + 1] = a2;
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ctx->gen_opparam_buf[pi + 2] = a3;
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tcg_emit_op(ctx, opc, pi);
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TCGOp *op = tcg_emit_op(ctx, opc);
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op->args[0] = a1;
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op->args[1] = a2;
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op->args[2] = a3;
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}
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void tcg_gen_op4(TCGContext *ctx, TCGOpcode opc, TCGArg a1,
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TCGArg a2, TCGArg a3, TCGArg a4)
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{
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int pi = ctx->gen_next_parm_idx;
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tcg_debug_assert(pi + 4 <= OPPARAM_BUF_SIZE);
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ctx->gen_next_parm_idx = pi + 4;
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ctx->gen_opparam_buf[pi + 0] = a1;
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ctx->gen_opparam_buf[pi + 1] = a2;
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ctx->gen_opparam_buf[pi + 2] = a3;
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ctx->gen_opparam_buf[pi + 3] = a4;
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tcg_emit_op(ctx, opc, pi);
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TCGOp *op = tcg_emit_op(ctx, opc);
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op->args[0] = a1;
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op->args[1] = a2;
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op->args[2] = a3;
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op->args[3] = a4;
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}
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void tcg_gen_op5(TCGContext *ctx, TCGOpcode opc, TCGArg a1,
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TCGArg a2, TCGArg a3, TCGArg a4, TCGArg a5)
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{
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int pi = ctx->gen_next_parm_idx;
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tcg_debug_assert(pi + 5 <= OPPARAM_BUF_SIZE);
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ctx->gen_next_parm_idx = pi + 5;
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ctx->gen_opparam_buf[pi + 0] = a1;
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ctx->gen_opparam_buf[pi + 1] = a2;
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ctx->gen_opparam_buf[pi + 2] = a3;
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ctx->gen_opparam_buf[pi + 3] = a4;
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ctx->gen_opparam_buf[pi + 4] = a5;
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tcg_emit_op(ctx, opc, pi);
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TCGOp *op = tcg_emit_op(ctx, opc);
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op->args[0] = a1;
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op->args[1] = a2;
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op->args[2] = a3;
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op->args[3] = a4;
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op->args[4] = a5;
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}
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void tcg_gen_op6(TCGContext *ctx, TCGOpcode opc, TCGArg a1, TCGArg a2,
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TCGArg a3, TCGArg a4, TCGArg a5, TCGArg a6)
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{
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int pi = ctx->gen_next_parm_idx;
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tcg_debug_assert(pi + 6 <= OPPARAM_BUF_SIZE);
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ctx->gen_next_parm_idx = pi + 6;
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ctx->gen_opparam_buf[pi + 0] = a1;
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ctx->gen_opparam_buf[pi + 1] = a2;
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ctx->gen_opparam_buf[pi + 2] = a3;
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ctx->gen_opparam_buf[pi + 3] = a4;
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ctx->gen_opparam_buf[pi + 4] = a5;
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ctx->gen_opparam_buf[pi + 5] = a6;
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tcg_emit_op(ctx, opc, pi);
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TCGOp *op = tcg_emit_op(ctx, opc);
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op->args[0] = a1;
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op->args[1] = a2;
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op->args[2] = a3;
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op->args[3] = a4;
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op->args[4] = a5;
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op->args[5] = a6;
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}
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void tcg_gen_mb(TCGContext *ctx, TCGBar mb_type)
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@ -467,7 +467,6 @@ void tcg_func_start(TCGContext *s)
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s->gen_op_buf[0].next = 1;
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s->gen_op_buf[0].prev = 0;
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s->gen_next_op_idx = 1;
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s->gen_next_parm_idx = 0;
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}
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static inline int temp_idx(TCGContext *s, TCGTemp *ts)
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@ -971,9 +970,10 @@ bool tcg_op_supported(TCGOpcode op)
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void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret,
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int nargs, TCGArg *args)
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{
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int i, real_args, nb_rets, pi, pi_first;
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int i, real_args, nb_rets, pi;
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unsigned sizemask, flags;
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TCGHelperInfo *info;
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TCGOp *op;
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info = g_hash_table_lookup(s->helpers, (gpointer)func);
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flags = info->flags;
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@ -986,11 +986,11 @@ void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret,
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int orig_sizemask = sizemask;
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int orig_nargs = nargs;
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TCGv_i64 retl, reth;
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TCGArg split_args[MAX_OPC_PARAM];
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TCGV_UNUSED_I64(retl);
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TCGV_UNUSED_I64(reth);
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if (sizemask != 0) {
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TCGArg *split_args = __builtin_alloca(sizeof(TCGArg) * nargs * 2);
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for (i = real_args = 0; i < nargs; ++i) {
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int is_64bit = sizemask & (1 << (i+1)*2);
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if (is_64bit) {
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@ -1025,7 +1025,19 @@ void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret,
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}
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#endif /* TCG_TARGET_EXTEND_ARGS */
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pi_first = pi = s->gen_next_parm_idx;
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i = s->gen_next_op_idx;
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tcg_debug_assert(i < OPC_BUF_SIZE);
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s->gen_op_buf[0].prev = i;
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s->gen_next_op_idx = i + 1;
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op = &s->gen_op_buf[i];
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/* Set links for sequential allocation during translation. */
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memset(op, 0, offsetof(TCGOp, args));
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op->opc = INDEX_op_call;
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op->prev = i - 1;
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op->next = i + 1;
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pi = 0;
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if (ret != TCG_CALL_DUMMY_ARG) {
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#if defined(__sparc__) && !defined(__arch64__) \
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&& !defined(CONFIG_TCG_INTERPRETER)
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@ -1035,31 +1047,33 @@ void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret,
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two return temporaries, and reassemble below. */
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retl = tcg_temp_new_i64(s);
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reth = tcg_temp_new_i64(s);
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s->gen_opparam_buf[pi++] = GET_TCGV_I64(reth);
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s->gen_opparam_buf[pi++] = GET_TCGV_I64(retl);
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op->args[pi++] = GET_TCGV_I64(reth);
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op->args[pi++] = GET_TCGV_I64(retl);
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nb_rets = 2;
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} else {
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s->gen_opparam_buf[pi++] = ret;
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op->args[pi++] = ret;
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nb_rets = 1;
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}
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#else
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if (TCG_TARGET_REG_BITS < 64 && (sizemask & 1)) {
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#ifdef HOST_WORDS_BIGENDIAN
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s->gen_opparam_buf[pi++] = ret + 1;
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s->gen_opparam_buf[pi++] = ret;
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op->args[pi++] = ret + 1;
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op->args[pi++] = ret;
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#else
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s->gen_opparam_buf[pi++] = ret;
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s->gen_opparam_buf[pi++] = ret + 1;
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op->args[pi++] = ret;
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op->args[pi++] = ret + 1;
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#endif
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nb_rets = 2;
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} else {
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s->gen_opparam_buf[pi++] = ret;
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op->args[pi++] = ret;
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nb_rets = 1;
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}
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#endif
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} else {
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nb_rets = 0;
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}
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op->callo = nb_rets;
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real_args = 0;
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for (i = 0; i < nargs; i++) {
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int is_64bit = sizemask & (1 << (i+1)*2);
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@ -1067,7 +1081,7 @@ void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret,
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#ifdef TCG_TARGET_CALL_ALIGN_ARGS
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/* some targets want aligned 64 bit args */
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if (real_args & 1) {
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s->gen_opparam_buf[pi++] = TCG_CALL_DUMMY_ARG;
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op->args[pi++] = TCG_CALL_DUMMY_ARG;
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real_args++;
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}
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#endif
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@ -1082,43 +1096,26 @@ void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret,
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have to get more complicated to differentiate between
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stack arguments and register arguments. */
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#if defined(HOST_WORDS_BIGENDIAN) != defined(TCG_TARGET_STACK_GROWSUP)
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s->gen_opparam_buf[pi++] = args[i] + 1;
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s->gen_opparam_buf[pi++] = args[i];
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op->args[pi++] = args[i] + 1;
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op->args[pi++] = args[i];
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#else
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s->gen_opparam_buf[pi++] = args[i];
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s->gen_opparam_buf[pi++] = args[i] + 1;
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op->args[pi++] = args[i];
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op->args[pi++] = args[i] + 1;
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#endif
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real_args += 2;
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continue;
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}
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s->gen_opparam_buf[pi++] = args[i];
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op->args[pi++] = args[i];
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real_args++;
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}
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s->gen_opparam_buf[pi++] = (uintptr_t)func;
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s->gen_opparam_buf[pi++] = flags;
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i = s->gen_next_op_idx;
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tcg_debug_assert(i < OPC_BUF_SIZE);
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tcg_debug_assert(pi <= OPPARAM_BUF_SIZE);
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/* Set links for sequential allocation during translation. */
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TCGOp op = {0};
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op.opc = INDEX_op_call;
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op.callo = nb_rets;
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op.calli = real_args;
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op.args = pi_first;
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op.prev = i - 1;
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op.next = i + 1;
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s->gen_op_buf[i] = op;
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/* Make sure the calli field didn't overflow. */
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tcg_debug_assert(s->gen_op_buf[i].calli == real_args);
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s->gen_op_buf[0].prev = i;
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s->gen_next_op_idx = i + 1;
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s->gen_next_parm_idx = pi;
|
||||
op->args[pi++] = (uintptr_t)func;
|
||||
op->args[pi++] = flags;
|
||||
op->calli = real_args;
|
||||
|
||||
/* Make sure the fields didn't overflow. */
|
||||
tcg_debug_assert(op->calli == real_args);
|
||||
tcg_debug_assert(pi <= ARRAY_SIZE(op->args));
|
||||
#if defined(__sparc__) && !defined(__arch64__) \
|
||||
&& !defined(CONFIG_TCG_INTERPRETER)
|
||||
/* Free all of the parts we allocated above. */
|
||||
|
|
@ -1333,7 +1330,7 @@ void tcg_dump_ops(TCGContext *s)
|
|||
op = &s->gen_op_buf[oi];
|
||||
c = op->opc;
|
||||
def = &s->tcg_op_defs[c];
|
||||
args = &s->gen_opparam_buf[op->args];
|
||||
args = op->args;
|
||||
|
||||
if (c == INDEX_op_insn_start) {
|
||||
col += qemu_log("%s ----", oi != s->gen_op_buf[0].next ? "\n" : "");
|
||||
|
|
@ -1627,19 +1624,15 @@ TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *old_op,
|
|||
TCGOpcode opc, int nargs)
|
||||
{
|
||||
int oi = s->gen_next_op_idx;
|
||||
int pi = s->gen_next_parm_idx;
|
||||
int prev = old_op->prev;
|
||||
int next = old_op - s->gen_op_buf;
|
||||
TCGOp *new_op;
|
||||
|
||||
tcg_debug_assert(oi < OPC_BUF_SIZE);
|
||||
tcg_debug_assert(pi + nargs <= OPPARAM_BUF_SIZE);
|
||||
s->gen_next_op_idx = oi + 1;
|
||||
s->gen_next_parm_idx = pi + nargs;
|
||||
|
||||
new_op = &s->gen_op_buf[oi];
|
||||
new_op->opc = opc;
|
||||
new_op->args = pi;
|
||||
new_op->prev = prev;
|
||||
new_op->next = next;
|
||||
s->gen_op_buf[prev].next = oi;
|
||||
|
|
@ -1652,19 +1645,15 @@ TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *old_op,
|
|||
TCGOpcode opc, int nargs)
|
||||
{
|
||||
int oi = s->gen_next_op_idx;
|
||||
int pi = s->gen_next_parm_idx;
|
||||
int prev = old_op - s->gen_op_buf;
|
||||
int next = old_op->next;
|
||||
TCGOp *new_op;
|
||||
|
||||
tcg_debug_assert(oi < OPC_BUF_SIZE);
|
||||
tcg_debug_assert(pi + nargs <= OPPARAM_BUF_SIZE);
|
||||
s->gen_next_op_idx = oi + 1;
|
||||
s->gen_next_parm_idx = pi + nargs;
|
||||
|
||||
new_op = &s->gen_op_buf[oi];
|
||||
new_op->opc = opc;
|
||||
new_op->args = pi;
|
||||
new_op->prev = prev;
|
||||
new_op->next = next;
|
||||
s->gen_op_buf[next].prev = oi;
|
||||
|
|
@ -1733,7 +1722,7 @@ static void liveness_pass_1(TCGContext *s, uint8_t *temp_state)
|
|||
TCGArg arg;
|
||||
|
||||
TCGOp * const op = &s->gen_op_buf[oi];
|
||||
TCGArg * const args = &s->gen_opparam_buf[op->args];
|
||||
TCGArg * const args = op->args;
|
||||
TCGOpcode opc = op->opc;
|
||||
const TCGOpDef *def = &s->tcg_op_defs[opc];
|
||||
|
||||
|
|
@ -1984,7 +1973,7 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *temp_state)
|
|||
|
||||
for (oi = s->gen_op_buf[0].next; oi != 0; oi = oi_next) {
|
||||
TCGOp *op = &s->gen_op_buf[oi];
|
||||
TCGArg *args = &s->gen_opparam_buf[op->args];
|
||||
TCGArg *args = op->args;
|
||||
TCGOpcode opc = op->opc;
|
||||
const TCGOpDef *def = &s->tcg_op_defs[opc];
|
||||
TCGLifeData arg_life = op->life;
|
||||
|
|
@ -2027,7 +2016,7 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *temp_state)
|
|||
? INDEX_op_ld_i32
|
||||
: INDEX_op_ld_i64);
|
||||
TCGOp *lop = tcg_op_insert_before(s, op, lopc, 3);
|
||||
TCGArg *largs = &s->gen_opparam_buf[lop->args];
|
||||
TCGArg *largs = lop->args;
|
||||
|
||||
largs[0] = dir;
|
||||
largs[1] = temp_idx(s, its->mem_base);
|
||||
|
|
@ -2099,7 +2088,7 @@ static bool liveness_pass_2(TCGContext *s, uint8_t *temp_state)
|
|||
? INDEX_op_st_i32
|
||||
: INDEX_op_st_i64);
|
||||
TCGOp *sop = tcg_op_insert_after(s, op, sopc, 3);
|
||||
TCGArg *sargs = &s->gen_opparam_buf[sop->args];
|
||||
TCGArg *sargs = sop->args;
|
||||
|
||||
sargs[0] = dir;
|
||||
sargs[1] = temp_idx(s, its->mem_base);
|
||||
|
|
@ -2920,7 +2909,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
|
|||
num_insns = -1;
|
||||
for (oi = s->gen_op_buf[0].next; oi != 0; oi = oi_next) {
|
||||
TCGOp * const op = &s->gen_op_buf[oi];
|
||||
TCGArg * const args = &s->gen_opparam_buf[op->args];
|
||||
TCGArg * const args = op->args;
|
||||
TCGOpcode opc = op->opc;
|
||||
const TCGOpDef *def = &s->tcg_op_defs[opc];
|
||||
TCGLifeData arg_life = op->life;
|
||||
|
|
|
|||
|
|
@ -54,8 +54,6 @@
|
|||
#define OPC_BUF_SIZE 640
|
||||
#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
|
||||
|
||||
#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
|
||||
|
||||
#define CPU_TEMP_BUF_NLONGS 128
|
||||
|
||||
/* Default target word size to pointer size. */
|
||||
|
|
@ -609,33 +607,33 @@ typedef struct TCGTempSet {
|
|||
#define SYNC_ARG 1
|
||||
typedef uint16_t TCGLifeData;
|
||||
|
||||
/* The layout here is designed to avoid crossing of a 32-bit boundary.
|
||||
If we do so, gcc adds padding, expanding the size to 12. */
|
||||
/* The layout here is designed to avoid a bitfield crossing of
|
||||
a 32-bit boundary, which would cause GCC to add extra padding. */
|
||||
typedef struct TCGOp {
|
||||
TCGOpcode opc : 8; /* 8 */
|
||||
|
||||
/* Index of the prev/next op, or 0 for the end of the list. */
|
||||
unsigned prev : 10; /* 18 */
|
||||
unsigned next : 10; /* 28 */
|
||||
|
||||
/* The number of out and in parameter for a call. */
|
||||
unsigned calli : 4; /* 32 */
|
||||
unsigned callo : 2; /* 34 */
|
||||
unsigned calli : 4; /* 12 */
|
||||
unsigned callo : 2; /* 14 */
|
||||
unsigned : 2; /* 16 */
|
||||
|
||||
/* Index of the arguments for this op, or 0 for zero-operand ops. */
|
||||
unsigned args : 14; /* 48 */
|
||||
/* Index of the prev/next op, or 0 for the end of the list. */
|
||||
unsigned prev : 16; /* 32 */
|
||||
unsigned next : 16; /* 48 */
|
||||
|
||||
/* Lifetime data of the operands. */
|
||||
unsigned life : 16; /* 64 */
|
||||
|
||||
/* Arguments for the opcode. */
|
||||
TCGArg args[MAX_OPC_PARAM];
|
||||
} TCGOp;
|
||||
|
||||
/* Make sure that we don't expand the structure without noticing. */
|
||||
QEMU_BUILD_BUG_ON(sizeof(TCGOp) != 8 + sizeof(TCGArg) * MAX_OPC_PARAM);
|
||||
|
||||
/* Make sure operands fit in the bitfields above. */
|
||||
QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8));
|
||||
QEMU_BUILD_BUG_ON(OPC_BUF_SIZE > (1 << 10));
|
||||
QEMU_BUILD_BUG_ON(OPPARAM_BUF_SIZE > (1 << 14));
|
||||
|
||||
/* Make sure that we don't overflow 64 bits without noticing. */
|
||||
QEMU_BUILD_BUG_ON(sizeof(TCGOp) > 8);
|
||||
QEMU_BUILD_BUG_ON(OPC_BUF_SIZE > (1 << 16));
|
||||
|
||||
/* pool based memory allocation */
|
||||
|
||||
|
|
@ -814,7 +812,6 @@ struct TCGContext {
|
|||
#endif
|
||||
|
||||
int gen_next_op_idx;
|
||||
int gen_next_parm_idx;
|
||||
|
||||
/* Code generation. Note that we specifically do not use tcg_insn_unit
|
||||
here, because there's too much arithmetic throughout that relies
|
||||
|
|
@ -852,7 +849,6 @@ struct TCGContext {
|
|||
TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS];
|
||||
|
||||
TCGOp gen_op_buf[OPC_BUF_SIZE];
|
||||
TCGArg gen_opparam_buf[OPPARAM_BUF_SIZE];
|
||||
|
||||
target_ulong gen_opc_pc[OPC_BUF_SIZE];
|
||||
uint16_t gen_opc_icount[OPC_BUF_SIZE];
|
||||
|
|
@ -989,8 +985,7 @@ struct TCGContext {
|
|||
|
||||
static inline void tcg_set_insn_param(TCGContext *tcg_ctx, int op_idx, int arg, TCGArg v)
|
||||
{
|
||||
int op_argi = tcg_ctx->gen_op_buf[op_idx].args;
|
||||
tcg_ctx->gen_opparam_buf[op_argi + arg] = v;
|
||||
tcg_ctx->gen_op_buf[op_idx].args[arg] = v;
|
||||
}
|
||||
|
||||
/* The number of opcodes emitted so far. */
|
||||
|
|
|
|||
|
|
@ -1361,6 +1361,8 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
|
|||
gen_intermediate_code(cpu, tb);
|
||||
tcg_ctx->cpu = NULL;
|
||||
|
||||
// Unicorn: FIXME: Needs to be amended to work with new TCG
|
||||
#if 0
|
||||
// Unicorn: when tracing block, patch block size operand for callback
|
||||
if (env->uc->size_arg != -1 && HOOK_EXISTS_BOUNDED(env->uc, UC_HOOK_BLOCK, tb->pc)) {
|
||||
if (env->uc->block_full) // block size is unknown
|
||||
|
|
@ -1368,6 +1370,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
|
|||
else
|
||||
*(tcg_ctx->gen_opparam_buf + env->uc->size_arg) = tb->size;
|
||||
}
|
||||
#endif
|
||||
|
||||
// UNICORN: Commented out
|
||||
//trace_translate_block(tb, tb->pc, tb->tc.ptr);
|
||||
|
|
|
|||
Loading…
Reference in a new issue