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target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0

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MFHC0 and MTHC0 used to handle EntryLo0 and EntryLo1 registers only,
and placing ELPA flag checks before switch statement were technically
correct. However, after adding handling more registers, these checks
should be moved to act only in cases of handling EntryLo0 and
EntryLo1.

Backports commit 59488dda1f16c0259bc2610d8d71686ef436c649 from qemu
This commit is contained in:
Yongbok Kim 2018-08-17 14:25:20 -04:00 committed by Lioncash
parent 9be6d4c6d2
commit eb775926fd
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 4 additions and 4 deletions
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8
qemu/target/mips/translate.c
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@ -4971,12 +4971,11 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
TCGContext *s = ctx->uc->tcg_ctx;
const char *rn = "invalid";
CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
switch (reg) {
case 2:
switch (sel) {
case 0:
CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
gen_mfhc0_entrylo(s, arg, offsetof(CPUMIPSState, CP0_EntryLo0));
rn = "EntryLo0";
break;
@ -4987,6 +4986,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 3:
switch (sel) {
case 0:
CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
gen_mfhc0_entrylo(s, arg, offsetof(CPUMIPSState, CP0_EntryLo1));
rn = "EntryLo1";
break;
@ -5042,12 +5042,11 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
const char *rn = "invalid";
uint64_t mask = ctx->PAMask >> 36;
CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
switch (reg) {
case 2:
switch (sel) {
case 0:
CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
tcg_gen_andi_tl(s, arg, arg, mask);
gen_mthc0_entrylo(s, arg, offsetof(CPUMIPSState, CP0_EntryLo0));
rn = "EntryLo0";
@ -5059,6 +5058,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 3:
switch (sel) {
case 0:
CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
tcg_gen_andi_tl(s, arg, arg, mask);
gen_mthc0_entrylo(s, arg, offsetof(CPUMIPSState, CP0_EntryLo1));
rn = "EntryLo1";