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target/arm: Update sve reduction vs simd_desc

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With the reduction operations, we intentionally increase maxsz to
the next power of 2, so as to fill out the reduction tree correctly.
Since e2e7168a214b, oprsz must equal maxsz, with exceptions for small
vectors, so this triggers an assertion for vector sizes > 32 that are
not themselves a power of 2.

Pass the power-of-two value in the simd_data field instead.

Backports c648c9b7e1ccff94b51ecbebe86a206952c47e75
This commit is contained in:
Richard Henderson 2021-03-30 14:44:52 -04:00 committed by Lioncash
parent 1b05fd82b7
commit ebacc7febd
2 changed files with 2 additions and 2 deletions
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2
qemu/target/arm/sve_helper.c
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@ -2895,7 +2895,7 @@ static TYPE NAME##_reduce(TYPE *data, float_status *status, uintptr_t n) \
} \ } \
uint64_t HELPER(NAME)(void *vn, void *vg, void *vs, uint32_t desc) \ uint64_t HELPER(NAME)(void *vn, void *vg, void *vs, uint32_t desc) \
{ \ { \
uintptr_t i, oprsz = simd_oprsz(desc), maxsz = simd_maxsz(desc); \ uintptr_t i, oprsz = simd_oprsz(desc), maxsz = simd_data(desc); \
TYPE data[sizeof(ARMVectorReg) / sizeof(TYPE)]; \ TYPE data[sizeof(ARMVectorReg) / sizeof(TYPE)]; \
for (i = 0; i < oprsz; ) { \ for (i = 0; i < oprsz; ) { \
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3)); \ uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3)); \

2
qemu/target/arm/translate-sve.c
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@ -3527,7 +3527,7 @@ static void do_reduce(DisasContext *s, arg_rpr_esz *a,
TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGContext *tcg_ctx = s->uc->tcg_ctx;
unsigned vsz = vec_full_reg_size(s); unsigned vsz = vec_full_reg_size(s);
unsigned p2vsz = pow2ceil(vsz); unsigned p2vsz = pow2ceil(vsz);
TCGv_i32 t_desc = tcg_const_i32(tcg_ctx, simd_desc(vsz, p2vsz, 0)); TCGv_i32 t_desc = tcg_const_i32(tcg_ctx, simd_desc(vsz, vsz, p2vsz));
TCGv_ptr t_zn, t_pg, status; TCGv_ptr t_zn, t_pg, status;
TCGv_i64 temp; TCGv_i64 temp;