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mips: Build fix
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b2f1326437
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@ -1049,7 +1049,7 @@ static inline void compute_hflags(CPUMIPSState *env)
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}
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}
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void cpu_mips_tlb_flush(CPUMIPSState *env, int flush_global);
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void cpu_mips_tlb_flush(CPUMIPSState *env);
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void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
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void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
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void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
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@ -211,12 +211,12 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
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return ret;
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}
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void cpu_mips_tlb_flush(CPUMIPSState *env, int flush_global)
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void cpu_mips_tlb_flush(CPUMIPSState *env)
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{
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MIPSCPU *cpu = mips_env_get_cpu(env);
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/* Flush qemu's TLB and discard all shadowed entries. */
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tlb_flush(CPU(cpu), flush_global);
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tlb_flush(CPU(cpu));
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env->tlb->tlb_in_use = env->tlb->nb_tlb;
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}
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@ -278,7 +278,7 @@ void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
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#if defined(TARGET_MIPS64)
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if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
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/* Access to at least one of the 64-bit segments has been disabled */
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cpu_mips_tlb_flush(env, 1);
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cpu_mips_tlb_flush(env);
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}
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#endif
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if (env->CP0_Config3 & (1 << CP0C3_MT)) {
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@ -2112,7 +2112,7 @@ void r4k_helper_tlbr(CPUMIPSState *env)
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/* If this will change the current ASID, flush qemu's TLB. */
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if (ASID != tlb->ASID)
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cpu_mips_tlb_flush (env, 1);
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cpu_mips_tlb_flush(env);
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r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
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