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mips: Build fix

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Lioncash 2018-03-01 22:54:17 -05:00
parent b2f1326437
commit ebae552174
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GPG key ID: 4E3C3CC1031BA9C7
3 changed files with 5 additions and 5 deletions
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2
qemu/target/mips/cpu.h
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@ -1049,7 +1049,7 @@ static inline void compute_hflags(CPUMIPSState *env)
} }
} }
void cpu_mips_tlb_flush(CPUMIPSState *env, int flush_global); void cpu_mips_tlb_flush(CPUMIPSState *env);
void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);

6
qemu/target/mips/helper.c
View file

@ -211,12 +211,12 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
return ret; return ret;
} }
void cpu_mips_tlb_flush(CPUMIPSState *env, int flush_global) void cpu_mips_tlb_flush(CPUMIPSState *env)
{ {
MIPSCPU *cpu = mips_env_get_cpu(env); MIPSCPU *cpu = mips_env_get_cpu(env);
/* Flush qemu's TLB and discard all shadowed entries. */ /* Flush qemu's TLB and discard all shadowed entries. */
tlb_flush(CPU(cpu), flush_global); tlb_flush(CPU(cpu));
env->tlb->tlb_in_use = env->tlb->nb_tlb; env->tlb->tlb_in_use = env->tlb->nb_tlb;
} }
@ -278,7 +278,7 @@ void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
/* Access to at least one of the 64-bit segments has been disabled */ /* Access to at least one of the 64-bit segments has been disabled */
cpu_mips_tlb_flush(env, 1); cpu_mips_tlb_flush(env);
} }
#endif #endif
if (env->CP0_Config3 & (1 << CP0C3_MT)) { if (env->CP0_Config3 & (1 << CP0C3_MT)) {

2
qemu/target/mips/op_helper.c
View file

@ -2112,7 +2112,7 @@ void r4k_helper_tlbr(CPUMIPSState *env)
/* If this will change the current ASID, flush qemu's TLB. */ /* If this will change the current ASID, flush qemu's TLB. */
if (ASID != tlb->ASID) if (ASID != tlb->ASID)
cpu_mips_tlb_flush (env, 1); cpu_mips_tlb_flush(env);
r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);