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target/riscv: vector single-width floating-point reduction instructions

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Backports 523547f19e3914f11543e2da03907c724f15cd5e
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LIU Zhiwei 2021-03-07 12:10:41 -05:00 committed by Lioncash
parent 798c1682f8
commit ebe125af76
7 changed files with 97 additions and 0 deletions
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9
qemu/header_gen.py
View file

@ -7239,6 +7239,15 @@ riscv_symbols = (
'helper_vwredsum_vs_b', 'helper_vwredsum_vs_b',
'helper_vwredsum_vs_h', 'helper_vwredsum_vs_h',
'helper_vwredsum_vs_w', 'helper_vwredsum_vs_w',
'helper_vfredsum_vs_h',
'helper_vfredsum_vs_w',
'helper_vfredsum_vs_d',
'helper_vfredmax_vs_h',
'helper_vfredmax_vs_w',
'helper_vfredmax_vs_d',
'helper_vfredmin_vs_h',
'helper_vfredmin_vs_w',
'helper_vfredmin_vs_d',
'pmp_hart_has_privs', 'pmp_hart_has_privs',
'pmpaddr_csr_read', 'pmpaddr_csr_read',
'pmpaddr_csr_write', 'pmpaddr_csr_write',

15
qemu/riscv32.h
View file

@ -4669,6 +4669,21 @@
#define helper_vredxor_vs_h helper_vredxor_vs_h_riscv32 #define helper_vredxor_vs_h helper_vredxor_vs_h_riscv32
#define helper_vredxor_vs_w helper_vredxor_vs_w_riscv32 #define helper_vredxor_vs_w helper_vredxor_vs_w_riscv32
#define helper_vredxor_vs_d helper_vredxor_vs_d_riscv32 #define helper_vredxor_vs_d helper_vredxor_vs_d_riscv32
#define helper_vwredsumu_vs_b helper_vwredsumu_vs_b_riscv32
#define helper_vwredsumu_vs_h helper_vwredsumu_vs_h_riscv32
#define helper_vwredsumu_vs_w helper_vwredsumu_vs_w_riscv32
#define helper_vwredsum_vs_b helper_vwredsum_vs_b_riscv32
#define helper_vwredsum_vs_h helper_vwredsum_vs_h_riscv32
#define helper_vwredsum_vs_w helper_vwredsum_vs_w_riscv32
#define helper_vfredsum_vs_h helper_vfredsum_vs_h_riscv32
#define helper_vfredsum_vs_w helper_vfredsum_vs_w_riscv32
#define helper_vfredsum_vs_d helper_vfredsum_vs_d_riscv32
#define helper_vfredmax_vs_h helper_vfredmax_vs_h_riscv32
#define helper_vfredmax_vs_w helper_vfredmax_vs_w_riscv32
#define helper_vfredmax_vs_d helper_vfredmax_vs_d_riscv32
#define helper_vfredmin_vs_h helper_vfredmin_vs_h_riscv32
#define helper_vfredmin_vs_w helper_vfredmin_vs_w_riscv32
#define helper_vfredmin_vs_d helper_vfredmin_vs_d_riscv32
#define pmp_hart_has_privs pmp_hart_has_privs_riscv32 #define pmp_hart_has_privs pmp_hart_has_privs_riscv32
#define pmpaddr_csr_read pmpaddr_csr_read_riscv32 #define pmpaddr_csr_read pmpaddr_csr_read_riscv32
#define pmpaddr_csr_write pmpaddr_csr_write_riscv32 #define pmpaddr_csr_write pmpaddr_csr_write_riscv32

15
qemu/riscv64.h
View file

@ -4669,6 +4669,21 @@
#define helper_vredxor_vs_h helper_vredxor_vs_h_riscv64 #define helper_vredxor_vs_h helper_vredxor_vs_h_riscv64
#define helper_vredxor_vs_w helper_vredxor_vs_w_riscv64 #define helper_vredxor_vs_w helper_vredxor_vs_w_riscv64
#define helper_vredxor_vs_d helper_vredxor_vs_d_riscv64 #define helper_vredxor_vs_d helper_vredxor_vs_d_riscv64
#define helper_vwredsumu_vs_b helper_vwredsumu_vs_b_riscv64
#define helper_vwredsumu_vs_h helper_vwredsumu_vs_h_riscv64
#define helper_vwredsumu_vs_w helper_vwredsumu_vs_w_riscv64
#define helper_vwredsum_vs_b helper_vwredsum_vs_b_riscv64
#define helper_vwredsum_vs_h helper_vwredsum_vs_h_riscv64
#define helper_vwredsum_vs_w helper_vwredsum_vs_w_riscv64
#define helper_vfredsum_vs_h helper_vfredsum_vs_h_riscv64
#define helper_vfredsum_vs_w helper_vfredsum_vs_w_riscv64
#define helper_vfredsum_vs_d helper_vfredsum_vs_d_riscv64
#define helper_vfredmax_vs_h helper_vfredmax_vs_h_riscv64
#define helper_vfredmax_vs_w helper_vfredmax_vs_w_riscv64
#define helper_vfredmax_vs_d helper_vfredmax_vs_d_riscv64
#define helper_vfredmin_vs_h helper_vfredmin_vs_h_riscv64
#define helper_vfredmin_vs_w helper_vfredmin_vs_w_riscv64
#define helper_vfredmin_vs_d helper_vfredmin_vs_d_riscv64
#define pmp_hart_has_privs pmp_hart_has_privs_riscv64 #define pmp_hart_has_privs pmp_hart_has_privs_riscv64
#define pmpaddr_csr_read pmpaddr_csr_read_riscv64 #define pmpaddr_csr_read pmpaddr_csr_read_riscv64
#define pmpaddr_csr_write pmpaddr_csr_write_riscv64 #define pmpaddr_csr_write pmpaddr_csr_write_riscv64

10
qemu/target/riscv/helper.h
View file

@ -1082,3 +1082,13 @@ DEF_HELPER_6(vwredsumu_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vwredsum_vs_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vwredsum_vs_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfredsum_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfredmax_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfredmax_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfredmax_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfredmin_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfredmin_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfredmin_vs_d, void, ptr, ptr, ptr, ptr, env, i32)

4
qemu/target/riscv/insn32.decode
View file

@ -541,6 +541,10 @@ vredmaxu_vs 000110 . ..... ..... 010 ..... 1010111 @r_vm
vredmax_vs 000111 . ..... ..... 010 ..... 1010111 @r_vm vredmax_vs 000111 . ..... ..... 010 ..... 1010111 @r_vm
vwredsumu_vs 110000 . ..... ..... 000 ..... 1010111 @r_vm vwredsumu_vs 110000 . ..... ..... 000 ..... 1010111 @r_vm
vwredsum_vs 110001 . ..... ..... 000 ..... 1010111 @r_vm vwredsum_vs 110001 . ..... ..... 000 ..... 1010111 @r_vm
# Vector ordered and unordered reduction sum
vfredsum_vs 0000-1 . ..... ..... 001 ..... 1010111 @r_vm
vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm
vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r vsetvl 1000000 ..... ..... 111 ..... 1010111 @r

5
qemu/target/riscv/insn_trans/trans_rvv.inc.c
View file

@ -2383,3 +2383,8 @@ GEN_OPIVV_TRANS(vredxor_vs, reduction_check)
/* Vector Widening Integer Reduction Instructions */ /* Vector Widening Integer Reduction Instructions */
GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_check) GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_check)
GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_check) GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_check)
/* Vector Single-Width Floating-Point Reduction Instructions */
GEN_OPFVV_TRANS(vfredsum_vs, reduction_check)
GEN_OPFVV_TRANS(vfredmax_vs, reduction_check)
GEN_OPFVV_TRANS(vfredmin_vs, reduction_check)

39
qemu/target/riscv/vector_helper.c
View file

@ -4393,3 +4393,42 @@ GEN_VEXT_RED(vwredsum_vs_w, int64_t, int32_t, H8, H4, DO_ADD, clearq)
GEN_VEXT_RED(vwredsumu_vs_b, uint16_t, uint8_t, H2, H1, DO_ADD, clearh) GEN_VEXT_RED(vwredsumu_vs_b, uint16_t, uint8_t, H2, H1, DO_ADD, clearh)
GEN_VEXT_RED(vwredsumu_vs_h, uint32_t, uint16_t, H4, H2, DO_ADD, clearl) GEN_VEXT_RED(vwredsumu_vs_h, uint32_t, uint16_t, H4, H2, DO_ADD, clearl)
GEN_VEXT_RED(vwredsumu_vs_w, uint64_t, uint32_t, H8, H4, DO_ADD, clearq) GEN_VEXT_RED(vwredsumu_vs_w, uint64_t, uint32_t, H8, H4, DO_ADD, clearq)
/* Vector Single-Width Floating-Point Reduction Instructions */
#define GEN_VEXT_FRED(NAME, TD, TS2, HD, HS2, OP, CLEAR_FN)\
void HELPER(NAME)(void *vd, void *v0, void *vs1, \
void *vs2, CPURISCVState *env, \
uint32_t desc) \
{ \
uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
uint32_t tot = env_archcpu(env)->cfg.vlen / 8; \
TD s1 = *((TD *)vs1 + HD(0)); \
\
for (i = 0; i < vl; i++) { \
TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
if (!vm && !vext_elem_mask(v0, mlen, i)) { \
continue; \
} \
s1 = OP(s1, (TD)s2, &env->fp_status); \
} \
*((TD *)vd + HD(0)) = s1; \
CLEAR_FN(vd, 1, sizeof(TD), tot); \
}
/* Unordered sum */
GEN_VEXT_FRED(vfredsum_vs_h, uint16_t, uint16_t, H2, H2, float16_add, clearh)
GEN_VEXT_FRED(vfredsum_vs_w, uint32_t, uint32_t, H4, H4, float32_add, clearl)
GEN_VEXT_FRED(vfredsum_vs_d, uint64_t, uint64_t, H8, H8, float64_add, clearq)
/* Maximum value */
GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, float16_maxnum, clearh)
GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, float32_maxnum, clearl)
GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, float64_maxnum, clearq)
/* Minimum value */
GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minnum, clearh)
GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minnum, clearl)
GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minnum, clearq)