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target/arm: Implement HCR.PTW

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If the HCR_EL2 PTW virtualizaiton configuration register bit
is set, then this means that a stage 2 Permission fault must
be generated if a stage 1 translation table access is made
to an address that is mapped as Device memory in stage 2.
Implement this.

Backports commit eadb2febf05452bd8062c4c7823d7d789142500c from qemu
This commit is contained in:
Peter Maydell 2018-11-10 09:25:54 -05:00 committed by Lioncash
parent 28fcb58c69
commit ebe442b1d4
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 20 additions and 1 deletions
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21
qemu/target/arm/helper.c
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@ -8345,9 +8345,20 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
hwaddr s2pa;
int s2prot;
int ret;
ARMCacheAttrs cacheattrs = {};
ARMCacheAttrs *pcacheattrs = NULL;
if (env->cp15.hcr_el2 & HCR_PTW) {
/*
* PTW means we must fault if this S1 walk touches S2 Device
* memory; otherwise we don't care about the attributes and can
* save the S2 translation the effort of computing them.
*/
pcacheattrs = &cacheattrs;
}
ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa,
&txattrs, &s2prot, &s2size, fi, NULL);
&txattrs, &s2prot, &s2size, fi, pcacheattrs);
if (ret) {
assert(fi->type != ARMFault_None);
fi->s2addr = addr;
@ -8355,6 +8366,14 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
fi->s1ptw = true;
return ~0;
}
if (pcacheattrs && (pcacheattrs->attrs & 0xf0) == 0) {
/* Access was to Device memory: generate Permission fault */
fi->type = ARMFault_Permission;
fi->s2addr = addr;
fi->stage2 = true;
fi->s1ptw = true;
return ~0;
}
addr = s2pa;
}
return addr;