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target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_*

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This is part of a reorganization to the set of mmu_idx.
This emphasizes that they apply to the EL1&0 regime.

The ultimate goal is

-- Non-secure regimes:
ARMMMUIdx_E10_0,
ARMMMUIdx_E20_0,
ARMMMUIdx_E10_1,
ARMMMUIdx_E2,
ARMMMUIdx_E20_2,

-- Secure regimes:
ARMMMUIdx_SE10_0,
ARMMMUIdx_SE10_1,
ARMMMUIdx_SE3,

-- Helper mmu_idx for non-secure EL1&0 stage1 and stage2
ARMMMUIdx_Stage2,
ARMMMUIdx_Stage1_E0,
ARMMMUIdx_Stage1_E1,

The 'S' prefix is reserved for "Secure". Unless otherwise specified,
each mmu_idx represents all stages of translation.

Backports commit 01b98b686460b3a0fb47125882e4f8d4268ac1b6 from qemu
This commit is contained in:
Richard Henderson 2020-03-21 14:09:12 -04:00 committed by Lioncash
parent 270d557a99
commit ec05f22e82
5 changed files with 31 additions and 31 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
qemu/target/arm/cpu.h
View file

@ -2800,8 +2800,8 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
#define ARM_MMU_IDX_COREIDX_MASK 0x7 #define ARM_MMU_IDX_COREIDX_MASK 0x7
typedef enum ARMMMUIdx { typedef enum ARMMMUIdx {
ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A, ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A,
ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A, ARMMMUIdx_E10_1 = 1 | ARM_MMU_IDX_A,
ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A, ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A,
ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A, ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A,
ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A,
@ -2826,8 +2826,8 @@ typedef enum ARMMMUIdx {
* for use when calling tlb_flush_by_mmuidx() and friends. * for use when calling tlb_flush_by_mmuidx() and friends.
*/ */
typedef enum ARMMMUIdxBit { typedef enum ARMMMUIdxBit {
ARMMMUIdxBit_S12NSE0 = 1 << 0, ARMMMUIdxBit_E10_0 = 1 << 0,
ARMMMUIdxBit_S12NSE1 = 1 << 1, ARMMMUIdxBit_E10_1 = 1 << 1,
ARMMMUIdxBit_S1E2 = 1 << 2, ARMMMUIdxBit_S1E2 = 1 << 2,
ARMMMUIdxBit_S1E3 = 1 << 3, ARMMMUIdxBit_S1E3 = 1 << 3,
ARMMMUIdxBit_S1SE0 = 1 << 4, ARMMMUIdxBit_S1SE0 = 1 << 4,

40
qemu/target/arm/helper.c
View file

@ -513,8 +513,8 @@ static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
CPUState *cs = env_cpu(env); CPUState *cs = env_cpu(env);
tlb_flush_by_mmuidx(cs, tlb_flush_by_mmuidx(cs,
ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_E10_1 |
ARMMMUIdxBit_S12NSE0 | ARMMMUIdxBit_E10_0 |
ARMMMUIdxBit_S2NS); ARMMMUIdxBit_S2NS);
} }
@ -526,8 +526,8 @@ static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
CPUState *cs = env_cpu(env); CPUState *cs = env_cpu(env);
tlb_flush_by_mmuidx_all_cpus_synced(cs, tlb_flush_by_mmuidx_all_cpus_synced(cs,
ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_E10_1 |
ARMMMUIdxBit_S12NSE0 | ARMMMUIdxBit_E10_0 |
ARMMMUIdxBit_S2NS); ARMMMUIdxBit_S2NS);
#endif #endif
} }
@ -2893,7 +2893,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
format64 = arm_s1_regime_using_lpae_format(env, mmu_idx); format64 = arm_s1_regime_using_lpae_format(env, mmu_idx);
if (arm_feature(env, ARM_FEATURE_EL2)) { if (arm_feature(env, ARM_FEATURE_EL2)) {
if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { if (mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_E10_1) {
format64 |= env->cp15.hcr_el2 & (HCR_VM | HCR_DC); format64 |= env->cp15.hcr_el2 & (HCR_VM | HCR_DC);
} else { } else {
format64 |= arm_current_el(env) == 2; format64 |= arm_current_el(env) == 2;
@ -2992,11 +2992,11 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
break; break;
case 4: case 4:
/* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
mmu_idx = ARMMMUIdx_S12NSE1; mmu_idx = ARMMMUIdx_E10_1;
break; break;
case 6: case 6:
/* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
mmu_idx = ARMMMUIdx_S12NSE0; mmu_idx = ARMMMUIdx_E10_0;
break; break;
default: default:
g_assert_not_reached(); g_assert_not_reached();
@ -3054,10 +3054,10 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
break; break;
case 4: /* AT S12E1R, AT S12E1W */ case 4: /* AT S12E1R, AT S12E1W */
mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1; mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_E10_1;
break; break;
case 6: /* AT S12E0R, AT S12E0W */ case 6: /* AT S12E0R, AT S12E0W */
mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0; mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_E10_0;
break; break;
default: default:
g_assert_not_reached(); g_assert_not_reached();
@ -3357,8 +3357,8 @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
/* Accesses to VTTBR may change the VMID so we must flush the TLB. */ /* Accesses to VTTBR may change the VMID so we must flush the TLB. */
if (raw_read(env, ri) != value) { if (raw_read(env, ri) != value) {
tlb_flush_by_mmuidx(cs, tlb_flush_by_mmuidx(cs,
ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_E10_1 |
ARMMMUIdxBit_S12NSE0 | ARMMMUIdxBit_E10_0 |
ARMMMUIdxBit_S2NS); ARMMMUIdxBit_S2NS);
raw_write(env, ri, value); raw_write(env, ri, value);
} }
@ -3719,7 +3719,7 @@ static int vae1_tlbmask(CPUARMState *env)
if (arm_is_secure_below_el3(env)) { if (arm_is_secure_below_el3(env)) {
return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
} else { } else {
return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0; return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0;
} }
} }
@ -3760,9 +3760,9 @@ static int alle1_tlbmask(CPUARMState *env)
if (arm_is_secure_below_el3(env)) { if (arm_is_secure_below_el3(env)) {
return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
} else if (arm_feature(env, ARM_FEATURE_EL2)) { } else if (arm_feature(env, ARM_FEATURE_EL2)) {
return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0 | ARMMMUIdxBit_S2NS; return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_S2NS;
} else { } else {
return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0; return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0;
} }
} }
@ -8660,8 +8660,8 @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
*/ */
static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx)
{ {
if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { if (mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_E10_1) {
mmu_idx += (ARMMMUIdx_S1NSE0 - ARMMMUIdx_S12NSE0); mmu_idx += (ARMMMUIdx_S1NSE0 - ARMMMUIdx_E10_0);
} }
return mmu_idx; return mmu_idx;
} }
@ -8706,8 +8706,8 @@ static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
return true; return true;
default: default:
return false; return false;
case ARMMMUIdx_S12NSE0: case ARMMMUIdx_E10_0:
case ARMMMUIdx_S12NSE1: case ARMMMUIdx_E10_1:
g_assert_not_reached(); g_assert_not_reached();
} }
} }
@ -10630,7 +10630,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
target_ulong *page_size, target_ulong *page_size,
ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
{ {
if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { if (mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_E10_1) {
/* /*
* Call ourselves recursively to do the stage 1 and then stage 2 * Call ourselves recursively to do the stage 1 and then stage 2
* translations. * translations.
@ -11168,7 +11168,7 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env)
if (el < 2 && arm_is_secure_below_el3(env)) { if (el < 2 && arm_is_secure_below_el3(env)) {
return ARMMMUIdx_S1SE0 + el; return ARMMMUIdx_S1SE0 + el;
} else { } else {
return ARMMMUIdx_S12NSE0 + el; return ARMMMUIdx_E10_0 + el;
} }
} }

4
qemu/target/arm/internals.h
View file

@ -810,8 +810,8 @@ static inline void arm_call_el_change_hook(ARMCPU *cpu)
static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
{ {
switch (mmu_idx) { switch (mmu_idx) {
case ARMMMUIdx_S12NSE0: case ARMMMUIdx_E10_0:
case ARMMMUIdx_S12NSE1: case ARMMMUIdx_E10_1:
case ARMMMUIdx_S1NSE0: case ARMMMUIdx_S1NSE0:
case ARMMMUIdx_S1NSE1: case ARMMMUIdx_S1NSE1:
case ARMMMUIdx_S1E2: case ARMMMUIdx_S1E2:

4
qemu/target/arm/translate-a64.c
View file

@ -114,8 +114,8 @@ static inline int get_a64_user_mem_index(DisasContext *s)
ARMMMUIdx useridx; ARMMMUIdx useridx;
switch (s->mmu_idx) { switch (s->mmu_idx) {
case ARMMMUIdx_S12NSE1: case ARMMMUIdx_E10_1:
useridx = ARMMMUIdx_S12NSE0; useridx = ARMMMUIdx_E10_0;
break; break;
case ARMMMUIdx_S1SE1: case ARMMMUIdx_S1SE1:
useridx = ARMMMUIdx_S1SE0; useridx = ARMMMUIdx_S1SE0;

6
qemu/target/arm/translate.c
View file

@ -147,9 +147,9 @@ static inline int get_a32_user_mem_index(DisasContext *s)
*/ */
switch (s->mmu_idx) { switch (s->mmu_idx) {
case ARMMMUIdx_S1E2: /* this one is UNPREDICTABLE */ case ARMMMUIdx_S1E2: /* this one is UNPREDICTABLE */
case ARMMMUIdx_S12NSE0: case ARMMMUIdx_E10_0:
case ARMMMUIdx_S12NSE1: case ARMMMUIdx_E10_1:
return arm_to_core_mmu_idx(ARMMMUIdx_S12NSE0); return arm_to_core_mmu_idx(ARMMMUIdx_E10_0);
case ARMMMUIdx_S1E3: case ARMMMUIdx_S1E3:
case ARMMMUIdx_S1SE0: case ARMMMUIdx_S1SE0:
case ARMMMUIdx_S1SE1: case ARMMMUIdx_S1SE1: