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https://github.com/yuzu-emu/unicorn.git
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target-arm: implement SCTLR.B, drop bswap_code
bswap_code is a CPU property of sorts ("is the iside endianness the opposite way round to TARGET_WORDS_BIGENDIAN?") but it is not the actual CPU state involved here which is SCTLR.B (set for BE32 binaries, clear for BE8). Replace bswap_code with SCTLR.B, and pass that to arm_ld*_code. The next patches will make data fetches honor both SCTLR.B and CPSR.E appropriately. Backports commit f9fd40ebe4f55e0048e002925b8d65e66d56e7a7 from qemu
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@ -25,10 +25,10 @@
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/* Load an instruction and return it in the standard little-endian order */
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static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr,
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bool do_swap)
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bool sctlr_b)
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{
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uint32_t insn = cpu_ldl_code(env, addr);
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if (do_swap) {
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if (bswap_code(sctlr_b)) {
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return bswap32(insn);
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}
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return insn;
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@ -36,10 +36,10 @@ static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr,
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/* Ditto, for a halfword (Thumb) instruction */
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static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
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bool do_swap)
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bool sctlr_b)
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{
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uint16_t insn = cpu_lduw_code(env, addr);
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if (do_swap) {
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if (bswap_code(sctlr_b)) {
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return bswap16(insn);
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}
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return insn;
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@ -481,9 +481,6 @@ typedef struct CPUARMState {
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uint32_t cregs[16];
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} iwmmxt;
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/* For mixed endian mode. */
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bool bswap_code;
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#if defined(CONFIG_USER_ONLY)
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/* For usermode syscall translation. */
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int eabi;
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@ -1951,8 +1948,8 @@ static inline bool arm_singlestep_active(CPUARMState *env)
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#define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT)
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#define ARM_TBFLAG_CONDEXEC_SHIFT 8
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#define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
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#define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
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#define ARM_TBFLAG_BSWAP_CODE_MASK (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
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#define ARM_TBFLAG_SCTLR_B_SHIFT 16
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#define ARM_TBFLAG_SCTLR_B_MASK (1 << ARM_TBFLAG_SCTLR_B_SHIFT)
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/* We store the bottom two bits of the CPAR as TB flags and handle
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* checks on the other bits at runtime
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*/
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@ -1988,13 +1985,34 @@ static inline bool arm_singlestep_active(CPUARMState *env)
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(((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
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#define ARM_TBFLAG_CONDEXEC(F) \
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(((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
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#define ARM_TBFLAG_BSWAP_CODE(F) \
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(((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT)
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#define ARM_TBFLAG_SCTLR_B(F) \
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(((F) & ARM_TBFLAG_SCTLR_B_MASK) >> ARM_TBFLAG_SCTLR_B_SHIFT)
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#define ARM_TBFLAG_XSCALE_CPAR(F) \
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(((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT)
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#define ARM_TBFLAG_NS(F) \
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(((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT)
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static inline bool bswap_code(bool sctlr_b)
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{
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#ifdef CONFIG_USER_ONLY
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/* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian.
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* The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0
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* would also end up as a mixed-endian mode with BE code, LE data.
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*/
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return
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#ifdef TARGET_WORDS_BIGENDIAN
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1 ^
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#endif
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sctlr_b;
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#else
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/* We do not implement BE32 mode for system-mode emulation, but
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* anyway it would always do little-endian accesses with
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* TARGET_WORDS_BIGENDIAN = 0.
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*/
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return 0;
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#endif
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}
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/* Return the exception level to which FP-disabled exceptions should
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* be taken, or 0 if FP is enabled.
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*/
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@ -2060,6 +2078,19 @@ static inline int fp_exception_el(CPUARMState *env)
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return 0;
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}
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static inline bool arm_sctlr_b(CPUARMState *env)
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{
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return
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/* We need not implement SCTLR.ITD in user-mode emulation, so
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* let linux-user ignore the fact that it conflicts with SCTLR_B.
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* This lets people run BE32 binaries with "-cpu any".
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*/
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#ifndef CONFIG_USER_ONLY
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!arm_feature(env, ARM_FEATURE_V7) &&
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#endif
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(env->cp15.sctlr_el[1] & SCTLR_B) != 0;
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}
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static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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target_ulong *cs_base, int *flags)
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{
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@ -2072,7 +2103,7 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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| (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
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| (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
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| (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
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| (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT);
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| (arm_sctlr_b(env) << ARM_TBFLAG_SCTLR_B_SHIFT);
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if (!(access_secure_reg(env))) {
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*flags |= ARM_TBFLAG_NS_MASK;
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}
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@ -5094,7 +5094,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
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#if 0
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if (semihosting_enabled) {
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int nr;
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nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
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nr = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) & 0xff;
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if (nr == 0xab) {
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env->regs[15] += 2;
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qemu_log_mask(CPU_LOG_INT,
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@ -5640,13 +5640,13 @@ static inline bool check_for_semihosting(CPUState *cs)
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case EXCP_SWI:
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/* Check for semihosting interrupt. */
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if (env->thumb) {
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imm = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
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imm = arm_lduw_code(env, env->regs[15] - 2, arm_sctlr_b(env))
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& 0xff;
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if (imm == 0xab) {
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break;
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}
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} else {
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imm = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
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imm = arm_ldl_code(env, env->regs[15] - 4, arm_sctlr_b(env))
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& 0xffffff;
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if (imm == 0x123456) {
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break;
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@ -5656,7 +5656,7 @@ static inline bool check_for_semihosting(CPUState *cs)
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case EXCP_BKPT:
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/* See if this is a semihosting syscall. */
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if (env->thumb) {
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imm = arm_lduw_code(env, env->regs[15], env->bswap_code)
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imm = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env))
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& 0xff;
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if (imm == 0xab) {
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env->regs[15] += 2;
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@ -11175,7 +11175,7 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
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return;
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}
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insn = arm_ldl_code(env, s->pc, s->bswap_code);
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insn = arm_ldl_code(env, s->pc, s->sctlr_b);
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s->insn = insn;
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s->pc += 4;
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@ -11250,11 +11250,7 @@ void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb)
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dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) &&
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!arm_el_is_aa64(env, 3);
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dc->thumb = 0;
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#if defined(TARGET_WORDS_BIGENDIAN)
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dc->bswap_code = 1;
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#else
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dc->bswap_code = 0;
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#endif
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dc->sctlr_b = 0;
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dc->condexec_mask = 0;
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dc->condexec_cond = 0;
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dc->mmu_idx = ARM_TBFLAG_MMUIDX(tb->flags);
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@ -7909,7 +7909,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) // qq
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if ((insn & 0x0ffffdff) == 0x01010000) {
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ARCH(6);
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/* setend */
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if (((insn >> 9) & 1) != s->bswap_code) {
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if (((insn >> 9) & 1) != bswap_code(s->sctlr_b)) {
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/* Dynamic endianness switching not implemented. */
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qemu_log_mask(LOG_UNIMP, "arm: unimplemented setend\n");
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goto illegal_op;
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/* Fall through to 32-bit decode. */
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}
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insn = arm_lduw_code(env, s->pc, s->bswap_code);
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insn = arm_lduw_code(env, s->pc, s->sctlr_b);
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s->pc += 2;
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insn |= (uint32_t)insn_hw1 << 16;
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}
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}
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insn = arm_lduw_code(env, s->pc, s->bswap_code);
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insn = arm_lduw_code(env, s->pc, s->sctlr_b);
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// Unicorn: trace this instruction on request
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if (HOOK_EXISTS_BOUNDED(s->uc, UC_HOOK_CODE, s->pc)) {
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case 2:
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/* setend */
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ARCH(6);
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if (((insn >> 3) & 1) != s->bswap_code) {
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if (((insn >> 3) & 1) != bswap_code(s->sctlr_b)) {
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/* Dynamic endianness switching not implemented. */
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qemu_log_mask(LOG_UNIMP, "arm: unimplemented setend\n");
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goto illegal_op;
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}
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/* This must be a Thumb insn */
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insn = arm_lduw_code(env, s->pc, s->bswap_code);
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insn = arm_lduw_code(env, s->pc, s->sctlr_b);
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if ((insn >> 11) >= 0x1d) {
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/* Top five bits 0b11101 / 0b11110 / 0b11111 : this is the
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dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) &&
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!arm_el_is_aa64(env, 3);
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dc->thumb = ARM_TBFLAG_THUMB(tb->flags); // qq
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dc->bswap_code = ARM_TBFLAG_BSWAP_CODE(tb->flags);
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dc->sctlr_b = ARM_TBFLAG_SCTLR_B(tb->flags);
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dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1;
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dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4;
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dc->mmu_idx = ARM_TBFLAG_MMUIDX(tb->flags);
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// imitate WFI instruction to halt emulation
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dc->is_jmp = DISAS_WFI;
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} else {
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insn = arm_ldl_code(env, dc->pc, dc->bswap_code);
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insn = arm_ldl_code(env, dc->pc, dc->sctlr_b);
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dc->pc += 4;
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disas_arm_insn(dc, insn);
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}
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@ -16,7 +16,7 @@ typedef struct DisasContext {
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struct TranslationBlock *tb;
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int singlestep_enabled;
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int thumb;
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int bswap_code;
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int sctlr_b;
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#if !defined(CONFIG_USER_ONLY)
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int user;
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#endif
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