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target/riscv: set-X-first mask bit

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Backports 81fbf7daf2eccadd6480b90db95a2e8c410d4414
This commit is contained in:
LIU Zhiwei 2021-03-07 12:24:41 -05:00 committed by Lioncash
parent 92d5ce9b66
commit ec24e09ce7
7 changed files with 108 additions and 0 deletions
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3
qemu/header_gen.py
View file

@ -7260,6 +7260,9 @@ riscv_symbols = (
'helper_vmxnor_mm',
'helper_vmpopc_m',
'helper_vmfirst_m',
'helper_vmsbf_m',
'helper_vmsif_m',
'helper_vmsof_m',
'pmp_hart_has_privs',
'pmpaddr_csr_read',
'pmpaddr_csr_write',

3
qemu/riscv32.h
View file

@ -4696,6 +4696,9 @@
#define helper_vmxnor_mm helper_vmxnor_mm_riscv32
#define helper_vmpopc_m helper_vmpopc_m_riscv32
#define helper_vmfirst_m helper_vmfirst_m_riscv32
#define helper_vmsbf_m helper_vmsbf_m_riscv32
#define helper_vmsif_m helper_vmsif_m_riscv32
#define helper_vmsof_m helper_vmsof_m_riscv32
#define pmp_hart_has_privs pmp_hart_has_privs_riscv32
#define pmpaddr_csr_read pmpaddr_csr_read_riscv32
#define pmpaddr_csr_write pmpaddr_csr_write_riscv32

3
qemu/riscv64.h
View file

@ -4696,6 +4696,9 @@
#define helper_vmxnor_mm helper_vmxnor_mm_riscv64
#define helper_vmpopc_m helper_vmpopc_m_riscv64
#define helper_vmfirst_m helper_vmfirst_m_riscv64
#define helper_vmsbf_m helper_vmsbf_m_riscv64
#define helper_vmsif_m helper_vmsif_m_riscv64
#define helper_vmsof_m helper_vmsof_m_riscv64
#define pmp_hart_has_privs pmp_hart_has_privs_riscv64
#define pmpaddr_csr_read pmpaddr_csr_read_riscv64
#define pmpaddr_csr_write pmpaddr_csr_write_riscv64

4
qemu/target/riscv/helper.h
View file

@ -1108,3 +1108,7 @@ DEF_HELPER_6(vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_4(vmpopc_m, tl, ptr, ptr, env, i32)
DEF_HELPER_4(vmfirst_m, tl, ptr, ptr, env, i32)
DEF_HELPER_5(vmsbf_m, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vmsif_m, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vmsof_m, void, ptr, ptr, ptr, env, i32)

3
qemu/target/riscv/insn32.decode
View file

@ -557,6 +557,9 @@ vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r
vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r
vmpopc_m 010100 . ..... ----- 010 ..... 1010111 @r2_vm
vmfirst_m 010101 . ..... ----- 010 ..... 1010111 @r2_vm
vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm
vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm
vmsof_m 010110 . ..... 00010 010 ..... 1010111 @r2_vm
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r

29
qemu/target/riscv/insn_trans/trans_rvv.inc.c
View file

@ -2495,3 +2495,32 @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
}
return false;
}
/* vmsbf.m set-before-first mask bit */
/* vmsif.m set-includ-first mask bit */
/* vmsof.m set-only-first mask bit */
#define GEN_M_TRANS(NAME) \
static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
{ \
TCGContext *tcg_ctx = s->uc->tcg_ctx; \
if (vext_check_isa_ill(s)) { \
uint32_t data = 0; \
gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \
TCGLabel *over = gen_new_label(tcg_ctx); \
tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_vl_risc, 0, over); \
\
data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_3_ptr(tcg_ctx, vreg_ofs(s, a->rd), \
vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \
tcg_ctx->cpu_env, 0, s->vlen / 8, data, fn); \
gen_set_label(tcg_ctx, over); \
return true; \
} \
return false; \
}
GEN_M_TRANS(vmsbf_m)
GEN_M_TRANS(vmsif_m)
GEN_M_TRANS(vmsof_m)

63
qemu/target/riscv/vector_helper.c
View file

@ -4557,3 +4557,66 @@ target_ulong HELPER(vmfirst_m)(void *v0, void *vs2, CPURISCVState *env,
}
return -1LL;
}
enum set_mask_type {
ONLY_FIRST = 1,
INCLUDE_FIRST,
BEFORE_FIRST,
};
static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
uint32_t desc, enum set_mask_type type)
{
uint32_t mlen = vext_mlen(desc);
uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen;
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
int i;
bool first_mask_bit = false;
for (i = 0; i < vl; i++) {
if (!vm && !vext_elem_mask(v0, mlen, i)) {
continue;
}
/* write a zero to all following active elements */
if (first_mask_bit) {
vext_set_elem_mask(vd, mlen, i, 0);
continue;
}
if (vext_elem_mask(vs2, mlen, i)) {
first_mask_bit = true;
if (type == BEFORE_FIRST) {
vext_set_elem_mask(vd, mlen, i, 0);
} else {
vext_set_elem_mask(vd, mlen, i, 1);
}
} else {
if (type == ONLY_FIRST) {
vext_set_elem_mask(vd, mlen, i, 0);
} else {
vext_set_elem_mask(vd, mlen, i, 1);
}
}
}
for (; i < vlmax; i++) {
vext_set_elem_mask(vd, mlen, i, 0);
}
}
void HELPER(vmsbf_m)(void *vd, void *v0, void *vs2, CPURISCVState *env,
uint32_t desc)
{
vmsetm(vd, v0, vs2, env, desc, BEFORE_FIRST);
}
void HELPER(vmsif_m)(void *vd, void *v0, void *vs2, CPURISCVState *env,
uint32_t desc)
{
vmsetm(vd, v0, vs2, env, desc, INCLUDE_FIRST);
}
void HELPER(vmsof_m)(void *vd, void *v0, void *vs2, CPURISCVState *env,
uint32_t desc)
{
vmsetm(vd, v0, vs2, env, desc, ONLY_FIRST);
}