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target/arm: Ignore fsr from get_phys_addr() in do_ats_write()

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In do_ats_write(), rather than using the FSR value from get_phys_addr(),
construct the PAR values using the information in the ARMMMUFaultInfo
struct. This allows us to create a PAR of the correct format regardless
of what the translation table format is.

For the moment we leave the condition for "when should this be a
64 bit PAR" as it was previously; this will need to be fixed to
properly support AArch32 Hyp mode.

Backports commit 5efe9ed45dec775ebe91ce72bd805ee780d16064 from qemu
This commit is contained in:
Peter Maydell 2018-03-05 14:01:23 -05:00 committed by Lioncash
parent 3a5701e030
commit ec686af668
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 10 additions and 6 deletions
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16
qemu/target/arm/helper.c
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@ -1923,7 +1923,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
hwaddr phys_addr; hwaddr phys_addr;
target_ulong page_size; target_ulong page_size;
int prot; int prot;
uint32_t fsr; uint32_t fsr_unused;
bool ret; bool ret;
uint64_t par64; uint64_t par64;
MemTxAttrs attrs = {0}; MemTxAttrs attrs = {0};
@ -1931,12 +1931,12 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
ARMCacheAttrs cacheattrs = {0}; ARMCacheAttrs cacheattrs = {0};
ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs, ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs,
&prot, &page_size, &fsr, &fi, &cacheattrs); &prot, &page_size, &fsr_unused, &fi, &cacheattrs);
/* TODO: this is not the correct condition to use to decide whether
* to report a PAR in 64-bit or 32-bit format.
*/
if (arm_s1_regime_using_lpae_format(env, mmu_idx)) { if (arm_s1_regime_using_lpae_format(env, mmu_idx)) {
/* fsr is a DFSR/IFSR value for the long descriptor /* Create a 64-bit PAR */
* translation table format, but with WnR always clear.
* Convert it to a 64-bit PAR.
*/
par64 = (1 << 11); /* LPAE bit always set */ par64 = (1 << 11); /* LPAE bit always set */
if (!ret) { if (!ret) {
par64 |= phys_addr & ~0xfffULL; par64 |= phys_addr & ~0xfffULL;
@ -1946,6 +1946,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
par64 |= (uint64_t)cacheattrs.attrs << 56; /* ATTR */ par64 |= (uint64_t)cacheattrs.attrs << 56; /* ATTR */
par64 |= cacheattrs.shareability << 7; /* SH */ par64 |= cacheattrs.shareability << 7; /* SH */
} else { } else {
uint32_t fsr = arm_fi_to_lfsc(&fi);
par64 |= 1; /* F */ par64 |= 1; /* F */
par64 |= (fsr & 0x3f) << 1; /* FS */ par64 |= (fsr & 0x3f) << 1; /* FS */
/* Note that S2WLK and FSTAGE are always zero, because we don't /* Note that S2WLK and FSTAGE are always zero, because we don't
@ -1970,6 +1972,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
par64 |= (1 << 9); /* NS */ par64 |= (1 << 9); /* NS */
} }
} else { } else {
uint32_t fsr = arm_fi_to_sfsc(&fi);
par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) | par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) |
((fsr & 0xf) << 1) | 1; ((fsr & 0xf) << 1) | 1;
} }