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target-arm: Fix handling of SDCR for 32-bit code

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Fix two issues with our implementation of the SDCR:
* it is only present from ARMv8 onwards
* it does not contain several of the trap bits present in its 64-bit
counterpart the MDCR_EL3

Put the register description in the right place so that it does not
get enabled for ARMv7 and earlier, and give it a write function so that
we can mask out the bits which should not be allowed to have an effect
if EL3 is 32-bit.

Backports commit a8d64e735182cbbb5dcc98f41656b118c45e57cc from qemu
This commit is contained in:
Peter Maydell 2018-02-20 22:26:56 -05:00 committed by Lioncash
parent 8477ed6389
commit ece364e7cc
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 15 additions and 5 deletions
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4
qemu/target-arm/cpu.h
View file

@ -604,6 +604,7 @@ void pmccntr_sync(CPUARMState *env);
#define MDCR_EDAD (1U << 20)
#define MDCR_SPME (1U << 17)
#define MDCR_SDD (1U << 16)
#define MDCR_SPD (3U << 14)
#define MDCR_TDRA (1U << 11)
#define MDCR_TDOSA (1U << 10)
#define MDCR_TDA (1U << 9)
@ -612,6 +613,9 @@ void pmccntr_sync(CPUARMState *env);
#define MDCR_TPM (1U << 6)
#define MDCR_TPMCR (1U << 5)
/* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
#define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
#define CPSR_M (0x1fU)
#define CPSR_T (1U << 5)
#define CPSR_F (1U << 6)

16
qemu/target-arm/helper.c
View file

@ -2733,6 +2733,12 @@ static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri,
return CP_ACCESS_OK;
}
static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
env->cp15.mdcr_el3 = value & SDCR_VALID_MASK;
}
static const ARMCPRegInfo v8_cp_reginfo[] = {
/* Minimal set of EL0-visible registers. This will need to be expanded
* significantly for system emulation of AArch64 CPUs.
@ -2960,6 +2966,11 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[BANK_UND]) },
{ "SPSR_FIQ", 0,4,3, 3,4,3, ARM_CP_STATE_AA64, ARM_CP_ALIAS,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[BANK_FIQ]) },
{ "MDCR_EL3", 0,1,3, 3,6,1, ARM_CP_STATE_AA64, 0,
PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mdcr_el3) },
{ "SDCR", 15,1,3, 0,0,1, 0, ARM_CP_ALIAS,
PL1_RW, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.mdcr_el3), {0, 0},
access_trap_aa32s_el1, NULL, sdcr_write },
REGINFO_SENTINEL
};
@ -3213,11 +3224,6 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
{ "SCR", 15,1,1, 0,0,0, 0,ARM_CP_ALIAS,
PL1_RW, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.scr_el3), {0, 0},
access_trap_aa32s_el1, NULL, scr_write, NULL, NULL, NULL },
{ "MDCR_EL3", 0,1,3, 3,6,1, ARM_CP_STATE_AA64, 0,
PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mdcr_el3) },
{ "SDCR", 15,1,3, 0,0,1, 0, ARM_CP_ALIAS,
PL1_RW, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.mdcr_el3), {0, 0},
access_trap_aa32s_el1 },
{ "SDER32_EL3", 0,1,1, 3,6,1, ARM_CP_STATE_AA64,0,
PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.sder) },
{ "SDER", 15,1,1, 0,0,1, 0,0,