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cpu: move cc->do_interrupt to tcg_ops

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Backports 0545608056a6161e7020cd7b9368d9636fa80051
This commit is contained in:
Claudio Fontana 2021-03-04 17:10:05 -05:00 committed by Lioncash
parent bc86f4377c
commit ee73443c7d
8 changed files with 12 additions and 12 deletions
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2
qemu/accel/tcg/cpu-exec.c
View file

@ -315,7 +315,7 @@ static inline bool cpu_handle_exception(struct uc_struct *uc, CPUState *cpu, int
loop */
#if defined(TARGET_I386)
CPUClass *cc = CPU_GET_CLASS(uc, cpu);
cc->do_interrupt(cpu);
cc->tcg_ops.do_interrupt(cpu);
#endif
*ret = cpu->exception_index;
cpu->exception_index = -1;

4
qemu/include/qom/cpu.h
View file

@ -104,6 +104,8 @@ typedef struct TcgCpuOperations {
void (*cpu_exec_exit)(CPUState *cpu);
/** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
/** @do_interrupt: Callback for interrupt handling. */
void (*do_interrupt)(CPUState *cpu);
/**
* @tlb_fill: Handle a softmmu tlb miss or user-only address fault
*
@ -129,7 +131,6 @@ typedef struct TcgCpuOperations {
* @reset: Callback to reset the #CPUState to its initial state.
* @reset_dump_flags: #CPUDumpFlags to use for reset logging.
* @has_work: Callback for checking if there is work to do.
* @do_interrupt: Callback for interrupt handling.
* @do_unassigned_access: Callback for unassigned access handling.
* (this is deprecated: new targets should use do_transaction_failed instead)
* @do_unaligned_access: Callback for unaligned access handling, if
@ -176,7 +177,6 @@ typedef struct CPUClass {
void (*reset)(CPUState *cpu);
int reset_dump_flags;
bool (*has_work)(CPUState *cpu);
void (*do_interrupt)(CPUState *cpu);
CPUUnassignedAccess do_unassigned_access;
void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
MMUAccessType access_type,

6
qemu/target/arm/cpu.c
View file

@ -583,7 +583,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
found:
cs->exception_index = excp_idx;
env->exception.target_el = target_el;
cc->do_interrupt(cs);
cc->tcg_ops.do_interrupt(cs);
return true;
}
@ -605,7 +605,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
if (interrupt_request & CPU_INTERRUPT_HARD
/*&& (armv7m_nvic_can_take_pending_exception(env->nvic)) */) {
cs->exception_index = EXCP_IRQ;
cc->do_interrupt(cs);
cc->tcg_ops.do_interrupt(cs);
ret = true;
}
return ret;
@ -2100,7 +2100,6 @@ static void arm_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *data
//cc->dump_state = arm_cpu_dump_state;
cc->set_pc = arm_cpu_set_pc;
#ifndef CONFIG_USER_ONLY
cc->do_interrupt = arm_cpu_do_interrupt;
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->asidx_from_attrs = arm_asidx_from_attrs;
// UNICORN: Commented out
@ -2118,6 +2117,7 @@ static void arm_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *data
#if !defined(CONFIG_USER_ONLY)
cc->do_transaction_failed = arm_cpu_do_transaction_failed;
cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
cc->tcg_ops.do_interrupt = arm_cpu_do_interrupt;
#endif
#endif
}

2
qemu/target/i386/cpu.c
View file

@ -5889,7 +5889,7 @@ static void x86_cpu_common_class_init(struct uc_struct *uc, ObjectClass *oc, voi
cc->tcg_ops.cpu_exec_enter = x86_cpu_exec_enter;
cc->tcg_ops.cpu_exec_exit = x86_cpu_exec_exit;
cc->tcg_ops.cpu_exec_interrupt = x86_cpu_exec_interrupt;
cc->do_interrupt = x86_cpu_do_interrupt;
cc->tcg_ops.do_interrupt = x86_cpu_do_interrupt;
#endif
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
cc->tcg_ops.debug_excp_handler = breakpoint_handler;

2
qemu/target/m68k/cpu.c
View file

@ -265,7 +265,7 @@ static void m68k_cpu_class_init(struct uc_struct *uc, ObjectClass *c, void *data
cc->class_by_name = m68k_cpu_class_by_name;
cc->has_work = m68k_cpu_has_work;
cc->do_interrupt = m68k_cpu_do_interrupt;
cc->tcg_ops.do_interrupt = m68k_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = m68k_cpu_exec_interrupt;
cc->set_pc = m68k_cpu_set_pc;
cc->tcg_ops.tlb_fill = m68k_cpu_tlb_fill;

4
qemu/target/mips/cpu.c
View file

@ -173,7 +173,6 @@ static void mips_cpu_class_init(struct uc_struct *uc, ObjectClass *c, void *data
cc->class_by_name = mips_cpu_class_by_name;
cc->has_work = mips_cpu_has_work;
cc->do_interrupt = mips_cpu_do_interrupt;
cc->set_pc = mips_cpu_set_pc;
#ifndef CONFIG_USER_ONLY
cc->do_transaction_failed = mips_cpu_do_transaction_failed;
@ -182,10 +181,11 @@ static void mips_cpu_class_init(struct uc_struct *uc, ObjectClass *c, void *data
#endif
#ifdef CONFIG_TCG
cc->tcg_ops.initialize = mips_tcg_init;
cc->tcg_ops.do_interrupt = mips_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = mips_cpu_exec_interrupt;
cc->tcg_ops.synchronize_from_tb = mips_cpu_synchronize_from_tb;
cc->tcg_ops.tlb_fill = mips_cpu_tlb_fill;
#endif
#endif /* CONFIG_TCG */
}
static void mips_cpu_cpudef_class_init(struct uc_struct *uc, ObjectClass *oc, void *data)

2
qemu/target/riscv/cpu.c
View file

@ -357,7 +357,7 @@ static void riscv_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *da
cc->class_by_name = riscv_cpu_class_by_name;
cc->has_work = riscv_cpu_has_work;
cc->do_interrupt = riscv_cpu_do_interrupt;
cc->tcg_ops.do_interrupt = riscv_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = riscv_cpu_exec_interrupt;
//cc->dump_state = riscv_cpu_dump_state;
cc->set_pc = riscv_cpu_set_pc;

2
qemu/target/sparc/cpu.c
View file

@ -840,7 +840,7 @@ static void sparc_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *da
cc->class_by_name = sparc_cpu_class_by_name;
cc->parse_features = sparc_cpu_parse_features;
cc->has_work = sparc_cpu_has_work;
cc->do_interrupt = sparc_cpu_do_interrupt;
cc->tcg_ops.do_interrupt = sparc_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = sparc_cpu_exec_interrupt;
//cc->dump_state = sparc_cpu_dump_state;
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)