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m68k: MOVEC insn. should generate exception if wrong CR is accessed

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Add CPU class detection for each CR type in the m68k_move_to/from helpers,
so that it throws and exception if an unsupported register is requested
for that CPU class.

Reclassified MOVEC insn. as only supported from 68010.

Backports 8df0e6aedad33c6746f4bc2a4d0cfdd432877084
This commit is contained in:
Lucien Murray-Pitts 2021-03-12 14:49:19 -05:00 committed by Lioncash
parent 0e992c16fd
commit f0846b7c34
4 changed files with 160 additions and 46 deletions
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15
qemu/target/m68k/cpu.c
View file

@ -111,6 +111,20 @@ static void m68000_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque)
m68k_set_feature(env, M68K_FEATURE_MOVEP);
}
/*
* Adds BKPT, MOVE-from-SR *now priv instr, and MOVEC, MOVES, RTD
*/
static void m68010_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque)
{
M68kCPU *cpu = M68K_CPU(uc, obj);
CPUM68KState *env = &cpu->env;
m68000_cpu_initfn(uc, obj, opaque);
m68k_set_feature(env, M68K_FEATURE_M68010);
m68k_set_feature(env, M68K_FEATURE_RTD);
m68k_set_feature(env, M68K_FEATURE_BKPT);
m68k_set_feature(env, M68K_FEATURE_MOVEC);
}
/* common features for 68020, 68030 and 68040 */
static void m680x0_cpu_common(CPUM68KState *env)
{
@ -342,6 +356,7 @@ static TypeInfo m68k_cpus_type_infos[] = {
.abstract = true,
},
DEFINE_M68K_CPU_TYPE("m68000", m68000_cpu_initfn),
DEFINE_M68K_CPU_TYPE("m68010", m68010_cpu_initfn),
DEFINE_M68K_CPU_TYPE("m68020", m68020_cpu_initfn),
DEFINE_M68K_CPU_TYPE("m68030", m68030_cpu_initfn),
DEFINE_M68K_CPU_TYPE("m68040", m68040_cpu_initfn),

1
qemu/target/m68k/cpu.h
View file

@ -466,6 +466,7 @@ void do_m68k_semihosting(CPUM68KState *env, int nr);
enum m68k_features {
/* Base m68k instruction set */
M68K_FEATURE_M68000,
M68K_FEATURE_M68010,
M68K_FEATURE_M68020,
M68K_FEATURE_M68030,
M68K_FEATURE_M68040,

122
qemu/target/m68k/helper.c
View file

@ -29,6 +29,14 @@
void raise_exception(CPUM68KState *env, int tt);
static void raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr)
{
CPUState *cs = env_cpu(env);
cs->exception_index = tt;
cpu_loop_exit_restore(cs, raddr);
}
void HELPER(cf_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)
{
switch (reg) {
@ -78,63 +86,106 @@ void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)
env->cacr = val & 0x80008000;
} else if (m68k_feature(env, M68K_FEATURE_M68060)) {
env->cacr = val & 0xf8e0e000;
} else {
break;
}
m68k_switch_sp(env);
return;
/* MC680[46]0 */
case M68K_CR_TC:
if (m68k_feature(env, M68K_FEATURE_M68040)
|| m68k_feature(env, M68K_FEATURE_M68060)) {
env->mmu.tcr = val;
return;
}
break;
/* MC68040 */
case M68K_CR_MMUSR:
if (m68k_feature(env, M68K_FEATURE_M68040)) {
env->mmu.mmusr = val;
return;
}
break;
/* MC680[46]0 */
case M68K_CR_SRP:
if (m68k_feature(env, M68K_FEATURE_M68040)
|| m68k_feature(env, M68K_FEATURE_M68060)) {
env->mmu.srp = val;
return;
}
break;
/* MC680[46]0 */
case M68K_CR_URP:
if (m68k_feature(env, M68K_FEATURE_M68040)
|| m68k_feature(env, M68K_FEATURE_M68060)) {
env->mmu.urp = val;
return;
/* MC680[46]0 */
}
break;
/* MC680[12346]0 */
case M68K_CR_USP:
env->sp[M68K_USP] = val;
return;
/* MC680[234]0 */
case M68K_CR_MSP:
if (m68k_feature(env, M68K_FEATURE_M68020)
|| m68k_feature(env, M68K_FEATURE_M68030)
|| m68k_feature(env, M68K_FEATURE_M68040)) {
env->sp[M68K_SSP] = val;
return;
}
break;
/* MC680[234]0 */
case M68K_CR_ISP:
if (m68k_feature(env, M68K_FEATURE_M68020)
|| m68k_feature(env, M68K_FEATURE_M68030)
|| m68k_feature(env, M68K_FEATURE_M68040)) {
env->sp[M68K_ISP] = val;
return;
}
break;
/* MC68040/MC68LC040 */
case M68K_CR_ITT0:
case M68K_CR_ITT0: /* MC68EC040 only: M68K_CR_IACR0 */
if (m68k_feature(env, M68K_FEATURE_M68040)) {
env->mmu.ttr[M68K_ITTR0] = val;
return;
}
break;
/* MC68040/MC68LC040 */
case M68K_CR_ITT1:
case M68K_CR_ITT1: /* MC68EC040 only: M68K_CR_IACR1 */
if (m68k_feature(env, M68K_FEATURE_M68040)) {
env->mmu.ttr[M68K_ITTR1] = val;
return;
}
break;
/* MC68040/MC68LC040 */
case M68K_CR_DTT0:
case M68K_CR_DTT0: /* MC68EC040 only: M68K_CR_DACR0 */
if (m68k_feature(env, M68K_FEATURE_M68040)) {
env->mmu.ttr[M68K_DTTR0] = val;
return;
}
break;
/* MC68040/MC68LC040 */
case M68K_CR_DTT1:
case M68K_CR_DTT1: /* MC68EC040 only: M68K_CR_DACR1 */
if (m68k_feature(env, M68K_FEATURE_M68040)) {
env->mmu.ttr[M68K_DTTR1] = val;
return;
}
break;
/* Unimplemented Registers */
case M68K_CR_CAAR:
case M68K_CR_PCR:
case M68K_CR_BUSCR:
break;
}
cpu_abort(env_cpu(env),
"Unimplemented control register write 0x%x = 0x%x\n",
reg, val);
}
/* Invalid control registers will generate an exception. */
raise_exception_ra(env, EXCP_ILLEGAL, 0);
return;
}
uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, uint32_t reg)
{
switch (reg) {
@ -149,50 +200,97 @@ uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, uint32_t reg)
return env->vbr;
/* MC680[2346]0 */
case M68K_CR_CACR:
if (m68k_feature(env, M68K_FEATURE_M68020)
|| m68k_feature(env, M68K_FEATURE_M68030)
|| m68k_feature(env, M68K_FEATURE_M68040)
|| m68k_feature(env, M68K_FEATURE_M68060)) {
return env->cacr;
}
break;
/* MC680[46]0 */
case M68K_CR_TC:
if (m68k_feature(env, M68K_FEATURE_M68040)
|| m68k_feature(env, M68K_FEATURE_M68060)) {
return env->mmu.tcr;
}
break;
/* MC68040 */
case M68K_CR_MMUSR:
if (m68k_feature(env, M68K_FEATURE_M68040)) {
return env->mmu.mmusr;
}
break;
/* MC680[46]0 */
case M68K_CR_SRP:
if (m68k_feature(env, M68K_FEATURE_M68040)
|| m68k_feature(env, M68K_FEATURE_M68060)) {
return env->mmu.srp;
}
break;
/* MC68040/MC68LC040 */
case M68K_CR_URP:
if (m68k_feature(env, M68K_FEATURE_M68040)
|| m68k_feature(env, M68K_FEATURE_M68060)) {
return env->mmu.urp;
}
break;
/* MC680[46]0 */
case M68K_CR_USP:
return env->sp[M68K_USP];
/* MC680[234]0 */
case M68K_CR_MSP:
if (m68k_feature(env, M68K_FEATURE_M68020)
|| m68k_feature(env, M68K_FEATURE_M68030)
|| m68k_feature(env, M68K_FEATURE_M68040)) {
return env->sp[M68K_SSP];
}
break;
/* MC680[234]0 */
case M68K_CR_ISP:
if (m68k_feature(env, M68K_FEATURE_M68020)
|| m68k_feature(env, M68K_FEATURE_M68030)
|| m68k_feature(env, M68K_FEATURE_M68040)) {
return env->sp[M68K_ISP];
/* MC68040/MC68LC040 */
case M68K_CR_URP:
return env->mmu.urp;
}
break;
/* MC68040/MC68LC040 */
case M68K_CR_ITT0: /* MC68EC040 only: M68K_CR_IACR0 */
if (m68k_feature(env, M68K_FEATURE_M68040)) {
return env->mmu.ttr[M68K_ITTR0];
}
break;
/* MC68040/MC68LC040 */
case M68K_CR_ITT1: /* MC68EC040 only: M68K_CR_IACR1 */
if (m68k_feature(env, M68K_FEATURE_M68040)) {
return env->mmu.ttr[M68K_ITTR1];
}
break;
/* MC68040/MC68LC040 */
case M68K_CR_DTT0: /* MC68EC040 only: M68K_CR_DACR0 */
if (m68k_feature(env, M68K_FEATURE_M68040)) {
return env->mmu.ttr[M68K_DTTR0];
}
break;
/* MC68040/MC68LC040 */
case M68K_CR_DTT1: /* MC68EC040 only: M68K_CR_DACR1 */
if (m68k_feature(env, M68K_FEATURE_M68040)) {
return env->mmu.ttr[M68K_DTTR1];
}
break;
/* Unimplemented Registers */
case M68K_CR_CAAR:
case M68K_CR_PCR:
case M68K_CR_BUSCR:
break;
}
cpu_abort(env_cpu(env), "Unimplemented control register read 0x%x\n",
reg);
}
/* Invalid control registers will generate an exception. */
raise_exception_ra(env, EXCP_ILLEGAL, 0);
return 0;
}
void HELPER(set_macsr)(CPUM68KState *env, uint32_t val)
{
uint32_t acc;

2
qemu/target/m68k/translate.c
View file

@ -6263,7 +6263,7 @@ void register_m68k_insns (CPUM68KState *env)
BASE(stop, 4e72, ffff);
BASE(rte, 4e73, ffff);
INSN(cf_movec, 4e7b, ffff, CF_ISA_A);
INSN(m68k_movec, 4e7a, fffe, M68000);
INSN(m68k_movec, 4e7a, fffe, MOVEC);
#endif
BASE(nop, 4e71, ffff);
INSN(rtd, 4e74, ffff, RTD);