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target-arm: Set correct syndrome for faults on MSR DAIF*, imm

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If the SCTLR.UMA trap bit is set then attempts by EL0 to update
the PSTATE DAIF bits via "MSR DAIFSet, imm" and "MSR DAIFClr, imm"
instructions will raise an exception. We were failing to set
the syndrome information for this exception, which meant that
it would be reported as a repeat of whatever the previous
exception was. Set the correct syndrome information.

Backports commit f2932df777dace044719dc2f394f5a5a8aa1b1cd from qemu
This commit is contained in:
Peter Maydell 2018-02-12 22:20:34 -05:00 committed by Lioncash
parent 6b2502ac4f
commit f0ed9c807c
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3
qemu/target-arm/op_helper.c
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@ -381,6 +381,9 @@ void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm)
*/
if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) {
env->exception.target_el = exception_target_el(env);
env->exception.syndrome = syn_aa64_sysregtrap(0, extract32(op, 0, 3),
extract32(op, 3, 3), 4,
imm, 0x1f, 0);
raise_exception(env, EXCP_UDEF);
}