yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2025-03-24 10:35:12 +00:00
Code Issues Packages Projects Releases Wiki Activity

target-arm: Implement missing AMAIR registers

Browse source 
The AMAIR registers are for providing auxiliary implementation
defined memory attributes. We already implemented a RAZ/WI
AMAIR_EL1; add the EL2 and EL3 versions for consistency.

Backports commit 2179ef958c81480b841ffa0aab5e265688ffd2b0 from qemu
This commit is contained in:
Peter Maydell 2018-02-15 08:54:53 -05:00 committed by Lioncash
parent 7d1422efc5
commit f1011035f0
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 11 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

11
qemu/target-arm/helper.c
View file

@ -2473,6 +2473,10 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
PL2_RW, 0, NULL, 0 }, PL2_RW, 0, NULL, 0 },
{ "HMAIR1", 0,10,2, 0,4,1, ARM_CP_STATE_AA32, ARM_CP_CONST, { "HMAIR1", 0,10,2, 0,4,1, ARM_CP_STATE_AA32, ARM_CP_CONST,
PL2_RW, 0, NULL, 0 }, PL2_RW, 0, NULL, 0 },
{ "AMAIR_EL2", 0,10,3, 3,4,0, ARM_CP_STATE_BOTH, ARM_CP_CONST,
PL2_RW, 0, NULL, 0 },
{ "HMAIR1", 0,10,3, 0,4,1, ARM_CP_STATE_AA32, ARM_CP_CONST,
PL2_RW, 0, NULL, 0 },
{ "TCR_EL2", 0,2,0, 3,4,2, ARM_CP_STATE_BOTH, ARM_CP_CONST, { "TCR_EL2", 0,2,0, 3,4,2, ARM_CP_STATE_BOTH, ARM_CP_CONST,
PL2_RW, 0, NULL, 0 }, PL2_RW, 0, NULL, 0 },
{ "SCTLR_EL2", 0,1,0, 3,4,0, ARM_CP_STATE_BOTH, ARM_CP_CONST, { "SCTLR_EL2", 0,1,0, 3,4,0, ARM_CP_STATE_BOTH, ARM_CP_CONST,
@ -2554,6 +2558,11 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mair_el[2]) }, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mair_el[2]) },
{ "HMAIR1", 0,10,2, 0,4,1, ARM_CP_STATE_AA32, ARM_CP_ALIAS, { "HMAIR1", 0,10,2, 0,4,1, ARM_CP_STATE_AA32, ARM_CP_ALIAS,
PL2_RW, 0, NULL, 0, offsetofhigh32(CPUARMState, cp15.mair_el[2]) }, PL2_RW, 0, NULL, 0, offsetofhigh32(CPUARMState, cp15.mair_el[2]) },
{ "AMAIR_EL2", 0,10,3, 3,4,0, ARM_CP_STATE_BOTH, ARM_CP_CONST,
PL2_RW, 0, NULL, 0 },
/* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
{ "HMAIR1", 0,10,3, 0,4,1, ARM_CP_STATE_AA32, ARM_CP_CONST,
PL2_RW, 0, NULL, 0 },
{ "TCR_EL2", 0,2,0, 3,4,2, ARM_CP_STATE_BOTH, 0, { "TCR_EL2", 0,2,0, 3,4,2, ARM_CP_STATE_BOTH, 0,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.tcr_el[2]), {0, 0}, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.tcr_el[2]), {0, 0},
NULL, NULL, vmsa_tcr_el1_write, NULL, raw_write, vmsa_ttbcr_reset }, NULL, NULL, vmsa_tcr_el1_write, NULL, raw_write, vmsa_ttbcr_reset },
@ -2647,6 +2656,8 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
cptr_access }, cptr_access },
{ "TPIDR_EL3", 0,13,0, 3,6,2, ARM_CP_STATE_AA64, 0, { "TPIDR_EL3", 0,13,0, 3,6,2, ARM_CP_STATE_AA64, 0,
PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.tpidr_el[3]) }, PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.tpidr_el[3]) },
{ "AMAIR_EL3", 0,10,3, 3,6,0, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL3_RW, 0, NULL, 0 },
REGINFO_SENTINEL REGINFO_SENTINEL
}; };