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tcg/mips: reserve a register for the guest_base.
Reserve a register for the guest_base using ppc code for reference. By doing so, we do not have to recompute it for every memory load. Backports commit 4df9cac57f5220c17d856292e90fce455f708421 from qemu
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53242e647d
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f1211b1c88
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@ -85,6 +85,10 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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#define TCG_TMP2 TCG_REG_T8
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#define TCG_TMP3 TCG_REG_T7
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#ifndef CONFIG_SOFTMMU
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#define TCG_GUEST_BASE_REG TCG_REG_S1
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#endif
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/* check if we really need so many registers :P */
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static const int tcg_target_reg_alloc_order[] = {
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/* Call saved registers. */
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@ -1502,8 +1506,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
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} else if (guest_base == (int16_t)guest_base) {
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tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
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} else {
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, guest_base);
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tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP0, addr_regl);
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tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
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}
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tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
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#endif
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@ -1656,8 +1659,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
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} else if (guest_base == (int16_t)guest_base) {
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tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
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} else {
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, guest_base);
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tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP0, addr_regl);
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tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
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}
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tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
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#endif
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@ -2467,6 +2469,13 @@ static void tcg_target_qemu_prologue(TCGContext *s)
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TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
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}
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#ifndef CONFIG_SOFTMMU
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if (guest_base) {
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
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tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
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}
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#endif
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/* Call generated code */
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tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0);
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/* delay slot */
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