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target/arm: Rearrange Floating-point data-processing (2 regs)
There are lots of special cases within these insns. Split the major argument decode/loading/saving into no_output (compares), rd_is_dp, and rm_is_dp. We still need to special case argument load for compare (rd as input, rm as zero) and vcvt fixed (rd as input+output), but lots of special cases do disappear. Now that we have a full switch at the beginning, hoist the ISA checks from the code generation. Backports commit e80941bd64cc388554770fd72334e9e7d459a1ef from qemu
This commit is contained in:
Richard Henderson
Lioncash
parent
dbe623dacc
commit
f16dcbe226
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@ -3761,52 +3761,108 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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}
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} else {
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/* data processing */
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bool rd_is_dp = dp;
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bool rm_is_dp = dp;
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bool no_output = false;
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/* The opcode is in bits 23, 21, 20 and 6. */
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op = ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) & 1);
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if (dp) {
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rn = VFP_SREG_N(insn);
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if (op == 15) {
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/* rn is opcode */
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rn = ((insn >> 15) & 0x1e) | ((insn >> 7) & 1);
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} else {
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/* rn is opcode, encoded as per VFP_SREG_N. */
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switch (rn) {
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case 0x00: /* vmov */
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case 0x01: /* vabs */
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case 0x02: /* vneg */
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case 0x03: /* vsqrt */
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break;
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case 0x04: /* vcvtb.f64.f16, vcvtb.f32.f16 */
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case 0x05: /* vcvtt.f64.f16, vcvtt.f32.f16 */
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/*
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* VCVTB, VCVTT: only present with the halfprec extension
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* UNPREDICTABLE if bit 8 is set prior to ARMv8
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* (we choose to UNDEF)
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*/
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if ((dp && !arm_dc_feature(s, ARM_FEATURE_V8)) ||
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!arm_dc_feature(s, ARM_FEATURE_VFP_FP16)) {
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return 1;
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}
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rm_is_dp = false;
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break;
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case 0x06: /* vcvtb.f16.f32, vcvtb.f16.f64 */
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case 0x07: /* vcvtt.f16.f32, vcvtt.f16.f64 */
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if ((dp && !arm_dc_feature(s, ARM_FEATURE_V8)) ||
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!arm_dc_feature(s, ARM_FEATURE_VFP_FP16)) {
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return 1;
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}
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rd_is_dp = false;
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break;
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case 0x08: case 0x0a: /* vcmp, vcmpz */
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case 0x09: case 0x0b: /* vcmpe, vcmpez */
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no_output = true;
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break;
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case 0x0c: /* vrintr */
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case 0x0d: /* vrintz */
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case 0x0e: /* vrintx */
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break;
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case 0x0f: /* vcvt double<->single */
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rd_is_dp = !dp;
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break;
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case 0x10: /* vcvt.fxx.u32 */
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case 0x11: /* vcvt.fxx.s32 */
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rm_is_dp = false;
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break;
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case 0x18: /* vcvtr.u32.fxx */
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case 0x19: /* vcvtz.u32.fxx */
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case 0x1a: /* vcvtr.s32.fxx */
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case 0x1b: /* vcvtz.s32.fxx */
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rd_is_dp = false;
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break;
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case 0x14: /* vcvt fp <-> fixed */
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case 0x15:
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case 0x16:
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case 0x17:
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case 0x1c:
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case 0x1d:
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case 0x1e:
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case 0x1f:
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if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
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return 1;
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}
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/* Immediate frac_bits has same format as SREG_M. */
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rm_is_dp = false;
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break;
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default:
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return 1;
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}
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} else if (dp) {
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/* rn is register number */
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VFP_DREG_N(rn, insn);
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}
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if (op == 15 && (rn == 15 || ((rn & 0x1c) == 0x18) ||
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((rn & 0x1e) == 0x6))) {
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/* Integer or single/half precision destination. */
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rd = VFP_SREG_D(insn);
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} else {
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if (rd_is_dp) {
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VFP_DREG_D(rd, insn);
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}
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if (op == 15 &&
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(((rn & 0x1c) == 0x10) || ((rn & 0x14) == 0x14) ||
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((rn & 0x1e) == 0x4))) {
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/* VCVT from int or half precision is always from S reg
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* regardless of dp bit. VCVT with immediate frac_bits
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* has same format as SREG_M.
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*/
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rm = VFP_SREG_M(insn);
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} else {
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rd = VFP_SREG_D(insn);
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}
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if (rm_is_dp) {
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VFP_DREG_M(rm, insn);
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}
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} else {
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rn = VFP_SREG_N(insn);
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if (op == 15 && rn == 15) {
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/* Double precision destination. */
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VFP_DREG_D(rd, insn);
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} else {
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rd = VFP_SREG_D(insn);
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}
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/* NB that we implicitly rely on the encoding for the frac_bits
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* in VCVT of fixed to float being the same as that of an SREG_M
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*/
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rm = VFP_SREG_M(insn);
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}
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veclen = s->vec_len;
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if (op == 15 && rn > 3)
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if (op == 15 && rn > 3) {
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veclen = 0;
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}
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/* Shut up compiler warnings. */
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delta_m = 0;
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@ -3842,55 +3898,28 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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/* Load the initial operands. */
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if (op == 15) {
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switch (rn) {
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case 16:
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case 17:
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/* Integer source */
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gen_mov_F0_vreg(s, 0, rm);
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break;
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case 8:
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case 9:
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/* Compare */
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case 0x08: case 0x09: /* Compare */
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gen_mov_F0_vreg(s, dp, rd);
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gen_mov_F1_vreg(s, dp, rm);
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break;
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case 10:
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case 11:
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/* Compare with zero */
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case 0x0a: case 0x0b: /* Compare with zero */
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gen_mov_F0_vreg(s, dp, rd);
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gen_vfp_F1_ld0(s, dp);
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break;
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case 20:
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case 21:
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case 22:
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case 23:
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case 28:
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case 29:
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case 30:
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case 31:
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case 0x14: /* vcvt fp <-> fixed */
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case 0x15:
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case 0x16:
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case 0x17:
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case 0x1c:
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case 0x1d:
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case 0x1e:
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case 0x1f:
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/* Source and destination the same. */
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gen_mov_F0_vreg(s, dp, rd);
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break;
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case 4:
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case 5:
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case 6:
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case 7:
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/* VCVTB, VCVTT: only present with the halfprec extension
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* UNPREDICTABLE if bit 8 is set prior to ARMv8
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* (we choose to UNDEF)
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*/
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if ((dp && !arm_dc_feature(s, ARM_FEATURE_V8)) ||
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!arm_dc_feature(s, ARM_FEATURE_VFP_FP16)) {
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return 1;
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}
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if (!extract32(rn, 1, 1)) {
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/* Half precision source. */
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gen_mov_F0_vreg(s, 0, rm);
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break;
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}
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/* Otherwise fall through */
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default:
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/* One source operand. */
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gen_mov_F0_vreg(s, dp, rm);
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gen_mov_F0_vreg(s, rm_is_dp, rm);
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break;
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}
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} else {
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@ -4169,10 +4198,11 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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break;
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}
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case 15: /* single<->double conversion */
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if (dp)
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if (dp) {
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gen_helper_vfp_fcvtsd(tcg_ctx, s->F0s, s->F0d, tcg_ctx->cpu_env);
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else
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} else {
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gen_helper_vfp_fcvtds(tcg_ctx, s->F0d, s->F0s, tcg_ctx->cpu_env);
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}
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break;
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case 16: /* fuito */
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gen_vfp_uito(s, dp, 0);
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@ -4181,27 +4211,15 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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gen_vfp_sito(s, dp, 0);
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break;
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case 20: /* fshto */
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if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
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return 1;
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}
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gen_vfp_shto(s, dp, 16 - rm, 0);
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break;
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case 21: /* fslto */
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if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
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return 1;
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}
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gen_vfp_slto(s, dp, 32 - rm, 0);
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break;
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case 22: /* fuhto */
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if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
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return 1;
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}
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gen_vfp_uhto(s, dp, 16 - rm, 0);
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break;
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case 23: /* fulto */
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if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
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return 1;
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}
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gen_vfp_ulto(s, dp, 32 - rm, 0);
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break;
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case 24: /* ftoui */
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@ -4217,57 +4235,34 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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gen_vfp_tosiz(s, dp, 0);
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break;
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case 28: /* ftosh */
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if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
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return 1;
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}
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gen_vfp_tosh(s, dp, 16 - rm, 0);
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break;
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case 29: /* ftosl */
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if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
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return 1;
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}
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gen_vfp_tosl(s, dp, 32 - rm, 0);
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break;
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case 30: /* ftouh */
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if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
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return 1;
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}
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gen_vfp_touh(s, dp, 16 - rm, 0);
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break;
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case 31: /* ftoul */
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if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
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return 1;
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}
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gen_vfp_toul(s, dp, 32 - rm, 0);
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break;
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default: /* undefined */
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return 1;
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g_assert_not_reached();
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}
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break;
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default: /* undefined */
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return 1;
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}
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/* Write back the result. */
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if (op == 15 && (rn >= 8 && rn <= 11)) {
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/* Comparison, do nothing. */
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} else if (op == 15 && dp && ((rn & 0x1c) == 0x18 ||
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(rn & 0x1e) == 0x6)) {
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/* VCVT double to int: always integer result.
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* VCVT double to half precision is always a single
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* precision result.
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*/
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gen_mov_vreg_F0(s, 0, rd);
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} else if (op == 15 && rn == 15) {
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/* conversion */
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gen_mov_vreg_F0(s, !dp, rd);
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} else {
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gen_mov_vreg_F0(s, dp, rd);
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/* Write back the result, if any. */
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if (!no_output) {
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gen_mov_vreg_F0(s, rd_is_dp, rd);
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}
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/* break out of the loop if we have finished */
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if (veclen == 0)
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if (veclen == 0) {
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break;
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}
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if (op == 15 && delta_m == 0) {
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/* single source one-many */
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