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target/arm: Replace offset with pc in gen_exception_internal_insn
The offset is variable depending on the instruction set. Passing in the actual value is clearer in intent. Backpors commit aee828e7541a5895669ade3a4b6978382b6b094a from qemu
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@ -394,9 +394,9 @@ static void gen_exception_internal(DisasContext *s, int excp)
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tcg_temp_free_i32(tcg_ctx, tcg_excp);
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}
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static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
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static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp)
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{
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gen_a64_set_pc_im(s, s->base.pc_next - offset);
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gen_a64_set_pc_im(s, pc);
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gen_exception_internal(s, excp);
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s->base.is_jmp = DISAS_NORETURN;
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}
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@ -2124,7 +2124,7 @@ static void disas_exc(DisasContext *s, uint32_t insn)
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break;
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}
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#endif
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gen_exception_internal_insn(s, 0, EXCP_SEMIHOST);
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gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST);
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} else {
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unsupported_encoding(s, insn);
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}
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@ -14562,7 +14562,7 @@ static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
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/* End the TB early; it likely won't be executed */
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dc->base.is_jmp = DISAS_TOO_MANY;
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} else {
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gen_exception_internal_insn(dc, 0, EXCP_DEBUG);
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gen_exception_internal_insn(dc, dc->base.pc_next, EXCP_DEBUG);
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/* The address covered by the breakpoint must be
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included in [tb->pc, tb->pc + tb->size) in order
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to for it to be properly cleared -- thus we
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@ -1315,10 +1315,10 @@ static inline void gen_smc(DisasContext *s)
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s->base.is_jmp = DISAS_SMC;
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}
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static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
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static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp)
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{
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gen_set_condexec(s);
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gen_set_pc_im(s, s->base.pc_next - offset);
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gen_set_pc_im(s, pc);
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gen_exception_internal(s, excp);
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s->base.is_jmp = DISAS_NORETURN;
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}
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@ -1372,7 +1372,7 @@ static inline void gen_hlt(DisasContext *s, int imm)
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s->current_el != 0 &&
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#endif
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(imm == (s->thumb ? 0x3c : 0xf000))) {
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gen_exception_internal_insn(s, 0, EXCP_SEMIHOST);
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gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST);
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return;
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}
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@ -12125,7 +12125,7 @@ static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
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/* End the TB early; it's likely not going to be executed */
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dc->base.is_jmp = DISAS_TOO_MANY;
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} else {
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gen_exception_internal_insn(dc, 0, EXCP_DEBUG);
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gen_exception_internal_insn(dc, dc->base.pc_next, EXCP_DEBUG);
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/* The address covered by the breakpoint must be
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included in [tb->pc, tb->pc + tb->size) in order
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to for it to be properly cleared -- thus we
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