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target/arm: Replace offset with pc in gen_exception_internal_insn

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The offset is variable depending on the instruction set.
Passing in the actual value is clearer in intent.

Backpors commit aee828e7541a5895669ade3a4b6978382b6b094a from qemu
This commit is contained in:
Richard Henderson 2019-11-18 20:01:34 -05:00 committed by Lioncash
parent 00fbadf637
commit f19b4df20d
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 8 additions and 8 deletions
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8
qemu/target/arm/translate-a64.c
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@ -394,9 +394,9 @@ static void gen_exception_internal(DisasContext *s, int excp)
tcg_temp_free_i32(tcg_ctx, tcg_excp);
}
static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp)
{
gen_a64_set_pc_im(s, s->base.pc_next - offset);
gen_a64_set_pc_im(s, pc);
gen_exception_internal(s, excp);
s->base.is_jmp = DISAS_NORETURN;
}
@ -2124,7 +2124,7 @@ static void disas_exc(DisasContext *s, uint32_t insn)
break;
}
#endif
gen_exception_internal_insn(s, 0, EXCP_SEMIHOST);
gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST);
} else {
unsupported_encoding(s, insn);
}
@ -14562,7 +14562,7 @@ static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
/* End the TB early; it likely won't be executed */
dc->base.is_jmp = DISAS_TOO_MANY;
} else {
gen_exception_internal_insn(dc, 0, EXCP_DEBUG);
gen_exception_internal_insn(dc, dc->base.pc_next, EXCP_DEBUG);
/* The address covered by the breakpoint must be
included in [tb->pc, tb->pc + tb->size) in order
to for it to be properly cleared -- thus we

8
qemu/target/arm/translate.c
View file

@ -1315,10 +1315,10 @@ static inline void gen_smc(DisasContext *s)
s->base.is_jmp = DISAS_SMC;
}
static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp)
{
gen_set_condexec(s);
gen_set_pc_im(s, s->base.pc_next - offset);
gen_set_pc_im(s, pc);
gen_exception_internal(s, excp);
s->base.is_jmp = DISAS_NORETURN;
}
@ -1372,7 +1372,7 @@ static inline void gen_hlt(DisasContext *s, int imm)
s->current_el != 0 &&
#endif
(imm == (s->thumb ? 0x3c : 0xf000))) {
gen_exception_internal_insn(s, 0, EXCP_SEMIHOST);
gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST);
return;
}
@ -12125,7 +12125,7 @@ static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
/* End the TB early; it's likely not going to be executed */
dc->base.is_jmp = DISAS_TOO_MANY;
} else {
gen_exception_internal_insn(dc, 0, EXCP_DEBUG);
gen_exception_internal_insn(dc, dc->base.pc_next, EXCP_DEBUG);
/* The address covered by the breakpoint must be
included in [tb->pc, tb->pc + tb->size) in order
to for it to be properly cleared -- thus we