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target-arm: Correctly reset SCTLR_EL3 for 64-bit CPUs

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The regdef for SCTRL_EL3 was incorrectly marked as being an
ARM_CP_ALIAS, with the remark that this was because the 32-bit
definition would take care of reset and migration. However the
intention for banked registers as documented in the comment in
add_cpreg_to_hashtable() is:

* 2) If ARMv8 is enabled then we can count on a 64-bit version
* taking care of the secure bank. This requires that separate
* 32 and 64-bit definitions are provided.

and so it marks the 32-bit secure banked version as an alias.
This results in the sctlr_s/sctlr_el[3] field never being reset
or migrated for a 64-bit CPU with EL3 enabled.

Fix this by removing the ARM_CP_ALIAS annotation from SCTLR_EL3.
Since this means it now needs a real reset value, move the regdef
into the same place that we define the 32-bit SCTLR.

Backports commit e24fdd238a159d830a9a65dd9b08f80fba9b9e06 from qemu
This commit is contained in:
Peter Maydell 2018-02-22 11:36:23 -05:00 committed by Lioncash
parent 224cbb008a
commit f1b5b5cea9
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 8 additions and 8 deletions
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16
qemu/target-arm/helper.c
View file

@ -3260,10 +3260,6 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
{ "MVBAR", 15,12,0, 0,0,1, 0,0, { "MVBAR", 15,12,0, 0,0,1, 0,0,
PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mvbar), {0, 0}, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mvbar), {0, 0},
access_trap_aa32s_el1, NULL, vbar_write }, access_trap_aa32s_el1, NULL, vbar_write },
{ "SCTLR_EL3", 0,1,0, 3,6,0, ARM_CP_STATE_AA64,
ARM_CP_ALIAS, /* reset handled by AArch32 view */
PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.sctlr_el[3]), {0, 0},
NULL, NULL, sctlr_write, NULL, raw_write, },
{ "TTBR0_EL3", 0,2,0, 3,6,0, ARM_CP_STATE_AA64,0, { "TTBR0_EL3", 0,2,0, 3,6,0, ARM_CP_STATE_AA64,0,
PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.ttbr0_el[3]), {0, 0}, PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.ttbr0_el[3]), {0, 0},
NULL, NULL, vmsa_ttbr_write }, NULL, NULL, vmsa_ttbr_write },
@ -3969,11 +3965,15 @@ void register_cp_regs_for_features(ARMCPU *cpu)
} }
if (arm_feature(env, ARM_FEATURE_EL3)) { if (arm_feature(env, ARM_FEATURE_EL3)) {
define_arm_cp_regs(cpu, el3_cp_reginfo); define_arm_cp_regs(cpu, el3_cp_reginfo);
ARMCPRegInfo rvbar = { ARMCPRegInfo el3_regs[] = {
"RVBAR_EL3", 0,12,0, 3,6,1, ARM_CP_STATE_AA64, { "RVBAR_EL3", 0,12,0, 3,6,1, ARM_CP_STATE_AA64,
ARM_CP_CONST, PL3_R, 0, NULL, cpu->rvbar ARM_CP_CONST, PL3_R, 0, NULL, cpu->rvbar },
{ "SCTLR_EL3", 0,1,0, 3,6,0, ARM_CP_STATE_AA64, 0,
PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.sctlr_el[3]), {0, 0},
NULL, NULL, sctlr_write, NULL, raw_write, },
}; };
define_one_arm_cp_reg(cpu, &rvbar);
define_arm_cp_regs(cpu, el3_regs);
} }
/* The behaviour of NSACR is sufficiently various that we don't /* The behaviour of NSACR is sufficiently various that we don't
* try to describe it in a single reginfo: * try to describe it in a single reginfo: