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target/arm: Move VLLDM and VLSTM to vfp.decode

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Now that we no longer have an early check for ARM_FEATURE_VFP,
we can use the proper ISA check in trans_VLLDM_VLSTM.

Backports commit dc778a6873f534817a13257be2acba3ca87ec015 from qemu
This commit is contained in:
Richard Henderson 2020-03-21 23:51:57 -04:00 committed by Lioncash
parent 7592564248
commit f1ce64857c
3 changed files with 51 additions and 45 deletions
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40
qemu/target/arm/translate-vfp.inc.c
View file

@ -2879,3 +2879,43 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
tcg_temp_free_ptr(tcg_ctx, fpst);
return true;
}
/*
* Decode VLLDM and VLSTM are nonstandard because:
* * if there is no FPU then these insns must NOP in
* Secure state and UNDEF in Nonsecure state
* * if there is an FPU then these insns do not have
* the usual behaviour that vfp_access_check() provides of
* being controlled by CPACR/NSACR enable bits or the
* lazy-stacking logic.
*/
static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i32 fptr;
if (!arm_dc_feature(s, ARM_FEATURE_M) ||
!arm_dc_feature(s, ARM_FEATURE_V8)) {
return false;
}
/* If not secure, UNDEF. */
if (!s->v8m_secure) {
return false;
}
/* If no fpu, NOP. */
if (!dc_isar_feature(aa32_vfp, s)) {
return true;
}
fptr = load_reg(s, a->rn);
if (a->l) {
gen_helper_v7m_vlldm(tcg_ctx, tcg_ctx->cpu_env, fptr);
} else {
gen_helper_v7m_vlstm(tcg_ctx, tcg_ctx->cpu_env, fptr);
}
tcg_temp_free_i32(tcg_ctx, fptr);
/* End the TB, because we have updated FP control bits */
s->base.is_jmp = DISAS_UPDATE;
return true;
}

54
qemu/target/arm/translate.c
View file

@ -11270,54 +11270,18 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
goto illegal_op; /* op0 = 0b11 : unallocated */
}
/*
* Decode VLLDM and VLSTM first: these are nonstandard because:
* * if there is no FPU then these insns must NOP in
* Secure state and UNDEF in Nonsecure state
* * if there is an FPU then these insns do not have
* the usual behaviour that disas_vfp_insn() provides of
* being controlled by CPACR/NSACR enable bits or the
* lazy-stacking logic.
*/
if (arm_dc_feature(s, ARM_FEATURE_V8) &&
(insn & 0xffa00f00) == 0xec200a00) {
/* 0b1110_1100_0x1x_xxxx_xxxx_1010_xxxx_xxxx
* - VLLDM, VLSTM
* We choose to UNDEF if the RAZ bits are non-zero.
*/
if (!s->v8m_secure || (insn & 0x0040f0ff)) {
if (disas_vfp_insn(s, insn)) {
if (((insn >> 8) & 0xe) == 10 &&
dc_isar_feature(aa32_fpsp_v2, s)) {
/* FP, and the CPU supports it */
goto illegal_op;
} else {
/* All other insns: NOCP */
gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
syn_uncategorized(),
default_exception_el(s));
}
if (arm_dc_feature(s, ARM_FEATURE_VFP)) {
TCGContext *tcg_ctx = s->uc->tcg_ctx;
uint32_t rn = (insn >> 16) & 0xf;
TCGv_i32 fptr = load_reg(s, rn);
if (extract32(insn, 20, 1)) {
gen_helper_v7m_vlldm(tcg_ctx, tcg_ctx->cpu_env, fptr);
} else {
gen_helper_v7m_vlstm(tcg_ctx, tcg_ctx->cpu_env, fptr);
}
tcg_temp_free_i32(tcg_ctx, fptr);
/* End the TB, because we have updated FP control bits */
s->base.is_jmp = DISAS_UPDATE;
}
break;
}
if (arm_dc_feature(s, ARM_FEATURE_VFP) &&
((insn >> 8) & 0xe) == 10) {
/* FP, and the CPU supports it */
if (disas_vfp_insn(s, insn)) {
goto illegal_op;
}
break;
}
/* All other insns: NOCP */
gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized(),
default_exception_el(s));
break;
}
if ((insn & 0xfe000a00) == 0xfc000800

2
qemu/target/arm/vfp.decode
View file

@ -242,3 +242,5 @@ VCVT_sp_int ---- 1110 1.11 110 s:1 .... 1010 rz:1 1.0 .... \
vd=%vd_sp vm=%vm_sp
VCVT_dp_int ---- 1110 1.11 110 s:1 .... 1011 rz:1 1.0 .... \
vd=%vd_sp vm=%vm_dp
VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000