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target/mips: Abstract mmu_idx from hflags

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The MIPS mmu_idx is sometimes calculated from hflags without an env
pointer available as cpu_mmu_index() requires.

Create a common hflags_mmu_index() for the purpose of this calculation
which can operate on any hflags, not just with an env pointer, and
update cpu_mmu_index() itself and gen_intermediate_code() to use it.

Also update debug_post_eret() and helper_mtc0_status() to log the MMU
mode with the status change (SM, UM, or nothing for kernel mode) based
on cpu_mmu_index() rather than directly testing hflags.

This will also allow the logic to be more easily updated when a new MMU
mode is added.

Backports commit b0fc6003224543d2bdb172eca752656a6223e4a1 from qemu
This commit is contained in:
James Hogan 2018-03-04 00:44:58 -05:00 committed by Lioncash
parent 8595d11eb4
commit f285157856
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
3 changed files with 10 additions and 4 deletions
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8
qemu/target/mips/cpu.h
View file

@ -698,9 +698,15 @@ extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
#define MMU_MODE1_SUFFIX _super #define MMU_MODE1_SUFFIX _super
#define MMU_MODE2_SUFFIX _user #define MMU_MODE2_SUFFIX _user
#define MMU_USER_IDX 2 #define MMU_USER_IDX 2
static inline int hflags_mmu_index(uint32_t hflags)
{
return hflags & MIPS_HFLAG_KSU;
}
static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch) static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch)
{ {
return env->hflags & MIPS_HFLAG_KSU; return hflags_mmu_index(env->hflags);
} }
static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)

4
qemu/target/mips/op_helper.c
View file

@ -1442,7 +1442,7 @@ void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
old, old & env->CP0_Cause & CP0Ca_IP_mask, old, old & env->CP0_Cause & CP0Ca_IP_mask,
val, val & env->CP0_Cause & CP0Ca_IP_mask, val, val & env->CP0_Cause & CP0Ca_IP_mask,
env->CP0_Cause); env->CP0_Cause);
switch (env->hflags & MIPS_HFLAG_KSU) { switch (cpu_mmu_index(env, false)) {
case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
case MIPS_HFLAG_KM: qemu_log("\n"); break; case MIPS_HFLAG_KM: qemu_log("\n"); break;
@ -2244,7 +2244,7 @@ static void debug_post_eret(CPUMIPSState *env)
qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
if (env->hflags & MIPS_HFLAG_DM) if (env->hflags & MIPS_HFLAG_DM)
qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
switch (env->hflags & MIPS_HFLAG_KSU) { switch (cpu_mmu_index(env, false)) {
case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
case MIPS_HFLAG_KM: qemu_log("\n"); break; case MIPS_HFLAG_KM: qemu_log("\n"); break;

2
qemu/target/mips/translate.c
View file

@ -20337,7 +20337,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
#ifdef CONFIG_USER_ONLY #ifdef CONFIG_USER_ONLY
ctx.mem_idx = MIPS_HFLAG_UM; ctx.mem_idx = MIPS_HFLAG_UM;
#else #else
ctx.mem_idx = ctx.hflags & MIPS_HFLAG_KSU; ctx.mem_idx = hflags_mmu_index(ctx.hflags);
#endif #endif
ctx.default_tcg_memop_mask = (ctx.insn_flags & ISA_MIPS32R6) ? ctx.default_tcg_memop_mask = (ctx.insn_flags & ISA_MIPS32R6) ?
MO_UNALN : MO_ALIGN; MO_UNALN : MO_ALIGN;