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cputlb: update TLB entry/index after tlb_fill
We are failing to take into account that tlb_fill() can cause a TLB resize, which renders prior TLB entry pointers/indices stale. Fix it by re-doing the TLB entry lookups immediately after tlb_fill. Fixes: 86e1eff8bc ("tcg: introduce dynamic TLB sizing", 2019-01-28) Backports commit 6d967cb86d5b4a60ba15b497126b621ce9ca6609 from qemu
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1b44fd94ac
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f31764dd5b
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@ -349,7 +349,8 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr)
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tlb_fill(cpu, addr, 0, MMU_INST_FETCH, mmu_idx, 0);
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index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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index = tlb_index(env, mmu_idx, addr);
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entry = tlb_entry(env, mmu_idx, addr);
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tlb_addr = env->tlb_table[mmu_idx][index].addr_code;
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if (!(tlb_addr & ~(TARGET_PAGE_MASK | TLB_RECHECK))) {
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/* RAM access. We can't handle this, so for now just stop */
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@ -528,7 +529,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
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tlb_fill(cpu, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr);
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index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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index = tlb_index(env, mmu_idx, addr);
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tlb_addr = env->tlb_table[mmu_idx][index].addr_read;
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if (!(tlb_addr & ~(TARGET_PAGE_MASK | TLB_RECHECK))) {
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/* RAM access */
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@ -584,7 +585,7 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
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tlb_fill(cpu, addr, size, MMU_DATA_STORE, mmu_idx, retaddr);
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index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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index = tlb_index(env, mmu_idx, addr);
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tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
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if (!(tlb_addr & ~(TARGET_PAGE_MASK | TLB_RECHECK))) {
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/* RAM access */
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@ -711,6 +712,8 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
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if (!VICTIM_TLB_HIT(addr_write, addr)) {
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tlb_fill(ENV_GET_CPU(env), addr, 1 << s_bits, MMU_DATA_STORE,
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mmu_idx, retaddr);
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index = tlb_index(env, mmu_idx, addr);
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tlbe = tlb_entry(env, mmu_idx, addr);
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}
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tlb_addr = tlb_addr_write(tlbe);
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}
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@ -226,6 +226,8 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr,
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if (!VICTIM_TLB_HIT(ADDR_READ, addr)) {
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tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, READ_ACCESS_TYPE,
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mmu_idx, retaddr);
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index = tlb_index(env, mmu_idx, addr);
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entry = tlb_entry(env, mmu_idx, addr);
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}
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tlb_addr = entry->ADDR_READ;
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}
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@ -412,6 +414,8 @@ WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr,
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if (!VICTIM_TLB_HIT(ADDR_READ, addr)) {
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tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, READ_ACCESS_TYPE,
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mmu_idx, retaddr);
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index = tlb_index(env, mmu_idx, addr);
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entry = tlb_entry(env, mmu_idx, addr);
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}
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tlb_addr = entry->ADDR_READ;
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}
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@ -585,6 +589,8 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
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if (!VICTIM_TLB_HIT(addr_write, addr)) {
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tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE,
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mmu_idx, retaddr);
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index = tlb_index(env, mmu_idx, addr);
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entry = tlb_entry(env, mmu_idx, addr);
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}
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tlb_addr = tlb_addr_write(entry);
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}
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@ -731,6 +737,8 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
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if (!VICTIM_TLB_HIT(addr_write, addr)) {
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tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE,
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mmu_idx, retaddr);
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index = tlb_index(env, mmu_idx, addr);
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entry = tlb_entry(env, mmu_idx, addr);
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}
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tlb_addr = tlb_addr_write(entry);
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}
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