tcg: Implement tcg_gen_gvec_3i()

Let's add tcg_gen_gvec_3i(), similar to tcg_gen_gvec_2i(), however
without introducing "gen_helper_gvec_3i *fnoi", as it isn't needed
for now.

Backports commit e1227bb6e59173117f094a6a13b998587b45c928 from qemu

qemu/aarch64.h

@@ -2842,6 +2842,7 @@
 #define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_aarch64
 #define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_aarch64
 #define tcg_gen_gvec_3 tcg_gen_gvec_3_aarch64
+#define tcg_gen_gvec_3i tcg_gen_gvec_3i_aarch64
 #define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_aarch64
 #define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_aarch64
 #define tcg_gen_gvec_4 tcg_gen_gvec_4_aarch64

qemu/aarch64eb.h

@@ -2842,6 +2842,7 @@
 #define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_aarch64eb
 #define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_aarch64eb
 #define tcg_gen_gvec_3 tcg_gen_gvec_3_aarch64eb
+#define tcg_gen_gvec_3i tcg_gen_gvec_3i_aarch64eb
 #define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_aarch64eb
 #define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_aarch64eb
 #define tcg_gen_gvec_4 tcg_gen_gvec_4_aarch64eb

qemu/arm.h

@@ -2842,6 +2842,7 @@
 #define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_arm
 #define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_arm
 #define tcg_gen_gvec_3 tcg_gen_gvec_3_arm
+#define tcg_gen_gvec_3i tcg_gen_gvec_3i_arm
 #define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_arm
 #define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_arm
 #define tcg_gen_gvec_4 tcg_gen_gvec_4_arm

qemu/armeb.h

@@ -2842,6 +2842,7 @@
 #define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_armeb
 #define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_armeb
 #define tcg_gen_gvec_3 tcg_gen_gvec_3_armeb
+#define tcg_gen_gvec_3i tcg_gen_gvec_3i_armeb
 #define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_armeb
 #define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_armeb
 #define tcg_gen_gvec_4 tcg_gen_gvec_4_armeb

qemu/header_gen.py

@@ -2848,6 +2848,7 @@ symbols = (
     'tcg_gen_gvec_2_ool',
     'tcg_gen_gvec_2_ptr',
     'tcg_gen_gvec_3',
+    'tcg_gen_gvec_3i',
     'tcg_gen_gvec_3_ool',
     'tcg_gen_gvec_3_ptr',
     'tcg_gen_gvec_4',

qemu/m68k.h

@@ -2842,6 +2842,7 @@
 #define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_m68k
 #define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_m68k
 #define tcg_gen_gvec_3 tcg_gen_gvec_3_m68k
+#define tcg_gen_gvec_3i tcg_gen_gvec_3i_m68k
 #define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_m68k
 #define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_m68k
 #define tcg_gen_gvec_4 tcg_gen_gvec_4_m68k

qemu/mips.h

@@ -2842,6 +2842,7 @@
 #define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_mips
 #define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_mips
 #define tcg_gen_gvec_3 tcg_gen_gvec_3_mips
+#define tcg_gen_gvec_3i tcg_gen_gvec_3i_mips
 #define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_mips
 #define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_mips
 #define tcg_gen_gvec_4 tcg_gen_gvec_4_mips

qemu/mips64.h

@@ -2842,6 +2842,7 @@
 #define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_mips64
 #define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_mips64
 #define tcg_gen_gvec_3 tcg_gen_gvec_3_mips64
+#define tcg_gen_gvec_3i tcg_gen_gvec_3i_mips64
 #define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_mips64
 #define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_mips64
 #define tcg_gen_gvec_4 tcg_gen_gvec_4_mips64

qemu/mips64el.h

@@ -2842,6 +2842,7 @@
 #define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_mips64el
 #define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_mips64el
 #define tcg_gen_gvec_3 tcg_gen_gvec_3_mips64el
+#define tcg_gen_gvec_3i tcg_gen_gvec_3i_mips64el
 #define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_mips64el
 #define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_mips64el
 #define tcg_gen_gvec_4 tcg_gen_gvec_4_mips64el

qemu/mipsel.h

@@ -2842,6 +2842,7 @@
 #define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_mipsel
 #define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_mipsel
 #define tcg_gen_gvec_3 tcg_gen_gvec_3_mipsel
+#define tcg_gen_gvec_3i tcg_gen_gvec_3i_mipsel
 #define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_mipsel
 #define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_mipsel
 #define tcg_gen_gvec_4 tcg_gen_gvec_4_mipsel

qemu/powerpc.h

@@ -2842,6 +2842,7 @@
 #define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_powerpc
 #define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_powerpc
 #define tcg_gen_gvec_3 tcg_gen_gvec_3_powerpc
+#define tcg_gen_gvec_3i tcg_gen_gvec_3i_powerpc
 #define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_powerpc
 #define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_powerpc
 #define tcg_gen_gvec_4 tcg_gen_gvec_4_powerpc

qemu/riscv32.h

@@ -2842,6 +2842,7 @@
 #define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_riscv32
 #define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_riscv32
 #define tcg_gen_gvec_3 tcg_gen_gvec_3_riscv32
+#define tcg_gen_gvec_3i tcg_gen_gvec_3i_riscv32
 #define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_riscv32
 #define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_riscv32
 #define tcg_gen_gvec_4 tcg_gen_gvec_4_riscv32

qemu/riscv64.h

@@ -2842,6 +2842,7 @@
 #define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_riscv64
 #define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_riscv64
 #define tcg_gen_gvec_3 tcg_gen_gvec_3_riscv64
+#define tcg_gen_gvec_3i tcg_gen_gvec_3i_riscv64
 #define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_riscv64
 #define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_riscv64
 #define tcg_gen_gvec_4 tcg_gen_gvec_4_riscv64

qemu/sparc.h

@@ -2842,6 +2842,7 @@
 #define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_sparc
 #define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_sparc
 #define tcg_gen_gvec_3 tcg_gen_gvec_3_sparc
+#define tcg_gen_gvec_3i tcg_gen_gvec_3i_sparc
 #define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_sparc
 #define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_sparc
 #define tcg_gen_gvec_4 tcg_gen_gvec_4_sparc

qemu/sparc64.h

@@ -2842,6 +2842,7 @@
 #define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_sparc64
 #define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_sparc64
 #define tcg_gen_gvec_3 tcg_gen_gvec_3_sparc64
+#define tcg_gen_gvec_3i tcg_gen_gvec_3i_sparc64
 #define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_sparc64
 #define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_sparc64
 #define tcg_gen_gvec_4 tcg_gen_gvec_4_sparc64

qemu/tcg/tcg-op-gvec.c

@@ -663,6 +663,29 @@ static void expand_3_i32(TCGContext *s, uint32_t dofs, uint32_t aofs,
     tcg_temp_free_i32(s, t0);
 }
 
+static void expand_3i_i32(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs,
+                          uint32_t oprsz, int32_t c, bool load_dest,
+                          void (*fni)(TCGContext *, TCGv_i32, TCGv_i32, TCGv_i32, int32_t))
+{
+    TCGv_i32 t0 = tcg_temp_new_i32(s);
+    TCGv_i32 t1 = tcg_temp_new_i32(s);
+    TCGv_i32 t2 = tcg_temp_new_i32(s);
+    uint32_t i;
+
+    for (i = 0; i < oprsz; i += 4) {
+        tcg_gen_ld_i32(s, t0, s->cpu_env, aofs + i);
+        tcg_gen_ld_i32(s, t1, s->cpu_env, bofs + i);
+        if (load_dest) {
+            tcg_gen_ld_i32(s, t2, s->cpu_env, dofs + i);
+        }
+        fni(s, t2, t0, t1, c);
+        tcg_gen_st_i32(s, t2, s->cpu_env, dofs + i);
+    }
+    tcg_temp_free_i32(s, t0);
+    tcg_temp_free_i32(s, t1);
+    tcg_temp_free_i32(s, t2);
+}
+
 /* Expand OPSZ bytes worth of three-operand operations using i32 elements.  */
 static void expand_4_i32(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs,
                          uint32_t cofs, uint32_t oprsz, bool write_aofs,
@@ -770,6 +793,29 @@ static void expand_3_i64(TCGContext *s, uint32_t dofs, uint32_t aofs,
     tcg_temp_free_i64(s, t0);
 }
 
+static void expand_3i_i64(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs,
+                          uint32_t oprsz, int64_t c, bool load_dest,
+                          void (*fni)(TCGContext *, TCGv_i64, TCGv_i64, TCGv_i64, int64_t))
+{
+    TCGv_i64 t0 = tcg_temp_new_i64(s);
+    TCGv_i64 t1 = tcg_temp_new_i64(s);
+    TCGv_i64 t2 = tcg_temp_new_i64(s);
+    uint32_t i;
+
+    for (i = 0; i < oprsz; i += 8) {
+        tcg_gen_ld_i64(s, t0, s->cpu_env, aofs + i);
+        tcg_gen_ld_i64(s, t1, s->cpu_env, bofs + i);
+        if (load_dest) {
+            tcg_gen_ld_i64(s, t2, s->cpu_env, dofs + i);
+        }
+        fni(s, t2, t0, t1, c);
+        tcg_gen_st_i64(s, t2, s->cpu_env, dofs + i);
+    }
+    tcg_temp_free_i64(s, t0);
+    tcg_temp_free_i64(s, t1);
+    tcg_temp_free_i64(s, t2);
+}
+
 /* Expand OPSZ bytes worth of three-operand operations using i64 elements.  */
 static void expand_4_i64(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs,
                          uint32_t cofs, uint32_t oprsz, bool write_aofs,
@@ -883,6 +929,35 @@ static void expand_3_vec(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t a
     tcg_temp_free_vec(s, t0);
 }
 
+/*
+ * Expand OPSZ bytes worth of three-vector operands and an immediate operand
+ * using host vectors.
+ */
+static void expand_3i_vec(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
+                          uint32_t bofs, uint32_t oprsz, uint32_t tysz,
+                          TCGType type, int64_t c, bool load_dest,
+                          void (*fni)(TCGContext *, unsigned, TCGv_vec, TCGv_vec, TCGv_vec,
+                                      int64_t))
+{
+    TCGv_vec t0 = tcg_temp_new_vec(s, type);
+    TCGv_vec t1 = tcg_temp_new_vec(s, type);
+    TCGv_vec t2 = tcg_temp_new_vec(s, type);
+    uint32_t i;
+
+    for (i = 0; i < oprsz; i += tysz) {
+        tcg_gen_ld_vec(s, t0, s->cpu_env, aofs + i);
+        tcg_gen_ld_vec(s, t1, s->cpu_env, bofs + i);
+        if (load_dest) {
+            tcg_gen_ld_vec(s, t2, s->cpu_env, dofs + i);
+        }
+        fni(s, vece, t2, t0, t1, c);
+        tcg_gen_st_vec(s, t2, s->cpu_env, dofs + i);
+    }
+    tcg_temp_free_vec(s, t0);
+    tcg_temp_free_vec(s, t1);
+    tcg_temp_free_vec(s, t2);
+}
+
 /* Expand OPSZ bytes worth of four-operand operations using host vectors.  */
 static void expand_4_vec(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
                          uint32_t bofs, uint32_t cofs, uint32_t oprsz,
@@ -1174,6 +1249,70 @@ void tcg_gen_gvec_3(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs,
     }
 }
 
+/* Expand a vector operation with three vectors and an immediate.  */
+void tcg_gen_gvec_3i(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs,
+                     uint32_t oprsz, uint32_t maxsz, int64_t c,
+                     const GVecGen3i *g)
+{
+    TCGType type;
+    uint32_t some;
+
+    check_size_align(oprsz, maxsz, dofs | aofs | bofs);
+    check_overlap_3(dofs, aofs, bofs, maxsz);
+
+    type = 0;
+    if (g->fniv) {
+        type = choose_vector_type(g->opc, g->vece, oprsz, g->prefer_i64);
+    }
+    switch (type) {
+    case TCG_TYPE_V256:
+        /*
+         * Recall that ARM SVE allows vector sizes that are not a
+         * power of 2, but always a multiple of 16.  The intent is
+         * that e.g. size == 80 would be expanded with 2x32 + 1x16.
+         */
+        some = QEMU_ALIGN_DOWN(oprsz, 32);
+        expand_3i_vec(s, g->vece, dofs, aofs, bofs, some, 32, TCG_TYPE_V256,
+                      c, g->load_dest, g->fniv);
+        if (some == oprsz) {
+            break;
+        }
+        dofs += some;
+        aofs += some;
+        bofs += some;
+        oprsz -= some;
+        maxsz -= some;
+        /* fallthru */
+    case TCG_TYPE_V128:
+        expand_3i_vec(s, g->vece, dofs, aofs, bofs, oprsz, 16, TCG_TYPE_V128,
+                      c, g->load_dest, g->fniv);
+        break;
+    case TCG_TYPE_V64:
+        expand_3i_vec(s, g->vece, dofs, aofs, bofs, oprsz, 8, TCG_TYPE_V64,
+                      c, g->load_dest, g->fniv);
+        break;
+
+    case 0:
+        if (g->fni8 && check_size_impl(oprsz, 8)) {
+            expand_3i_i64(s, dofs, aofs, bofs, oprsz, c, g->load_dest, g->fni8);
+        } else if (g->fni4 && check_size_impl(oprsz, 4)) {
+            expand_3i_i32(s, dofs, aofs, bofs, oprsz, c, g->load_dest, g->fni4);
+        } else {
+            assert(g->fno != NULL);
+            tcg_gen_gvec_3_ool(s, dofs, aofs, bofs, oprsz, maxsz, c, g->fno);
+            return;
+        }
+        break;
+
+    default:
+        g_assert_not_reached();
+    }
+
+    if (oprsz < maxsz) {
+        expand_clr(s, dofs + oprsz, maxsz - oprsz);
+    }
+}
+
 /* Expand a vector four-operand operation.  */
 void tcg_gen_gvec_4(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs,
                     uint32_t oprsz, uint32_t maxsz, const GVecGen4 *g)

qemu/tcg/tcg-op-gvec.h

@@ -164,6 +164,27 @@ typedef struct {
     bool load_dest;
 } GVecGen3;
 
+typedef struct {
+    /*
+     * Expand inline as a 64-bit or 32-bit integer. Only one of these will be
+     * non-NULL.
+     */
+    void (*fni8)(TCGContext *, TCGv_i64, TCGv_i64, TCGv_i64, int64_t);
+    void (*fni4)(TCGContext *, TCGv_i32, TCGv_i32, TCGv_i32, int32_t);
+    /* Expand inline with a host vector type.  */
+    void (*fniv)(TCGContext *, unsigned, TCGv_vec, TCGv_vec, TCGv_vec, int64_t);
+    /* Expand out-of-line helper w/descriptor, data in descriptor.  */
+    gen_helper_gvec_3 *fno;
+    /* The opcode, if any, to which this corresponds.  */
+    TCGOpcode opc;
+    /* The vector element size, if applicable.  */
+    uint8_t vece;
+    /* Prefer i64 to v64.  */
+    bool prefer_i64;
+    /* Load dest as a 3rd source operand.  */
+    bool load_dest;
+} GVecGen3i;
+
 typedef struct {
     /* Expand inline as a 64-bit or 32-bit integer.
        Only one of these will be non-NULL.  */
@@ -193,6 +214,9 @@ void tcg_gen_gvec_2s(TCGContext *, uint32_t dofs, uint32_t aofs, uint32_t oprsz,
                      uint32_t maxsz, TCGv_i64 c, const GVecGen2s *);
 void tcg_gen_gvec_3(TCGContext *, uint32_t dofs, uint32_t aofs, uint32_t bofs,
                     uint32_t oprsz, uint32_t maxsz, const GVecGen3 *);
+void tcg_gen_gvec_3i(TCGContext *, uint32_t dofs, uint32_t aofs, uint32_t bofs,
+                     uint32_t oprsz, uint32_t maxsz, int64_t c,
+                     const GVecGen3i *);
 void tcg_gen_gvec_4(TCGContext *, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs,
                     uint32_t oprsz, uint32_t maxsz, const GVecGen4 *);
 

qemu/x86_64.h

@@ -2842,6 +2842,7 @@
 #define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_x86_64
 #define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_x86_64
 #define tcg_gen_gvec_3 tcg_gen_gvec_3_x86_64
+#define tcg_gen_gvec_3i tcg_gen_gvec_3i_x86_64
 #define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_x86_64
 #define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_x86_64
 #define tcg_gen_gvec_4 tcg_gen_gvec_4_x86_64