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target/arm: Fix select for aa64_va_parameters_both
Select should always be 0 for a regime with one range. Backports commit 71d181640a1a9470f074fa28600ca85587e2ca6b from qemu
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@ -10096,13 +10096,8 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va,
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bool tbi, tbid, epd, hpd, using16k, using64k;
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bool tbi, tbid, epd, hpd, using16k, using64k;
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int select, tsz;
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int select, tsz;
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/*
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* Bit 55 is always between the two regions, and is canonical for
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* determining if address tagging is enabled.
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*/
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select = extract64(va, 55, 1);
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if (!regime_has_2_ranges(mmu_idx)) {
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if (!regime_has_2_ranges(mmu_idx)) {
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select = 0;
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tsz = extract32(tcr, 0, 6);
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tsz = extract32(tcr, 0, 6);
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using64k = extract32(tcr, 14, 1);
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using64k = extract32(tcr, 14, 1);
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using16k = extract32(tcr, 15, 1);
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using16k = extract32(tcr, 15, 1);
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@ -10115,23 +10110,30 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va,
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tbid = extract32(tcr, 29, 1);
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tbid = extract32(tcr, 29, 1);
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}
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}
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epd = false;
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epd = false;
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} else if (!select) {
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tsz = extract32(tcr, 0, 6);
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epd = extract32(tcr, 7, 1);
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using64k = extract32(tcr, 14, 1);
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using16k = extract32(tcr, 15, 1);
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tbi = extract64(tcr, 37, 1);
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hpd = extract64(tcr, 41, 1);
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tbid = extract64(tcr, 51, 1);
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} else {
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} else {
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int tg = extract32(tcr, 30, 2);
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/*
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using16k = tg == 1;
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* Bit 55 is always between the two regions, and is canonical for
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using64k = tg == 3;
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* determining if address tagging is enabled.
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tsz = extract32(tcr, 16, 6);
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*/
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epd = extract32(tcr, 23, 1);
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select = extract64(va, 55, 1);
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tbi = extract64(tcr, 38, 1);
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if (!select) {
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hpd = extract64(tcr, 42, 1);
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tsz = extract32(tcr, 0, 6);
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tbid = extract64(tcr, 52, 1);
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epd = extract32(tcr, 7, 1);
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using64k = extract32(tcr, 14, 1);
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using16k = extract32(tcr, 15, 1);
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tbi = extract64(tcr, 37, 1);
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hpd = extract64(tcr, 41, 1);
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tbid = extract64(tcr, 51, 1);
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} else {
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int tg = extract32(tcr, 30, 2);
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using16k = tg == 1;
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using64k = tg == 3;
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tsz = extract32(tcr, 16, 6);
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epd = extract32(tcr, 23, 1);
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tbi = extract64(tcr, 38, 1);
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hpd = extract64(tcr, 42, 1);
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tbid = extract64(tcr, 52, 1);
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}
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}
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}
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tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */
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tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */
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tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */
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tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */
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