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unicorn_arm: Don't steamroll CPSR bits defined as RAZ/SBZP

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Prevents bits from being set that should always read as zero according
to the ARM architecture reference manual.
This commit is contained in:
Lioncash 2019-04-26 07:51:35 -04:00
parent 8b2a0554cf
commit f419015aa3
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 10 additions and 4 deletions
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14
qemu/target/arm/unicorn_arm.c
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@ -69,9 +69,12 @@ int arm_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun
case UC_ARM_REG_APSR:
*(int32_t *)value = cpsr_read(state) & CPSR_NZCV;
break;
case UC_ARM_REG_CPSR:
*(int32_t *)value = cpsr_read(state);
case UC_ARM_REG_CPSR: {
// Bits 20-23 should always read as zero.
const uint32_t mask = 0xFF0FFFFF;
*(int32_t *)value = cpsr_read(state) & mask;
break;
}
//case UC_ARM_REG_SP:
case UC_ARM_REG_R13:
*(int32_t *)value = state->regs[13];
@ -134,9 +137,12 @@ int arm_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, i
case UC_ARM_REG_APSR:
cpsr_write(state, *(uint32_t *)value, CPSR_NZCV, CPSRWriteRaw);
break;
case UC_ARM_REG_CPSR:
cpsr_write(state, *(uint32_t *)value, ~0, CPSRWriteRaw);
case UC_ARM_REG_CPSR: {
// Bits 20-23 are considered reserved and should always read as zero.
const uint32_t mask = 0xFF0FFFFF;
cpsr_write(state, *(uint32_t *)value, mask, CPSRWriteRaw);
break;
}
//case UC_ARM_REG_SP:
case UC_ARM_REG_R13:
state->regs[13] = *(uint32_t *)value;