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armv7m: FAULTMASK should be 0 on reset

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For M profile CPUs, FAULTMASK should be 0 on reset, like PRIMASK.
QEMU stores FAULTMASK in the PSTATE F bit, so (as with PRIMASK in the
I bit) we have to clear these to undo the A profile default of 1.

Update the comment accordingly and move it so that it's closer to the
code it's referring to.

Backports commit dc7abe4d65ad39390b2db120f5ad18f8f6576f8b from qemu
This commit is contained in:
Michael Davidsaver 2018-03-02 13:55:56 -05:00 committed by Lioncash
parent 8a6d746aef
commit f42f22ec02
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 6 additions and 4 deletions
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10
qemu/target/arm/cpu.c
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@ -173,9 +173,7 @@ static void arm_cpu_reset(CPUState *s)
/* SVC mode with interrupts disabled. */
env->uncached_cpsr = ARM_CPU_MODE_SVC;
env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
/* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
* clear at reset. Initial SP and PC are loaded from ROM.
*/
if (arm_feature(env, ARM_FEATURE_M)) {
uint32_t initial_msp; /* Loaded from 0x0 */
uint32_t initial_pc; /* Loaded from 0x4 */
@ -184,7 +182,10 @@ static void arm_cpu_reset(CPUState *s)
env->v7m.secure = true;
}
env->daif &= ~PSTATE_I;
/* For M profile we store FAULTMASK and PRIMASK in the
* PSTATE F and I bits; these are both clear at reset.
*/
env->daif &= ~(PSTATE_I | PSTATE_F);
/* The reset value of this bit is IMPDEF, but ARM recommends
* that it resets to 1, so QEMU always does that rather than making
@ -192,6 +193,7 @@ static void arm_cpu_reset(CPUState *s)
*/
env->v7m.ccr = R_V7M_CCR_STKALIGN_MASK;
#if 0
/* Load the initial SP and PC from the vector table at address 0 */
uint8_t *rom;
rom = rom_ptr(0);
if (rom) {