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https://github.com/yuzu-emu/unicorn.git
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target/arm: Drop manual handling of set/clear_helper_retaddr
Since we converted back to cpu_*_data_ra, we do not need to do this ourselves. Backports commit f32e2ab65f3a0fc03d58936709e5a565c4b0db50 from qemu
This commit is contained in:
Richard Henderson
Lioncash
parent
2e03f74a53
commit
f430a399d4
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@ -4095,13 +4095,6 @@ static intptr_t max_for_page(target_ulong base, intptr_t mem_off,
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return MIN(split, mem_max - mem_off) + mem_off;
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}
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static inline void set_helper_retaddr(uintptr_t ra)
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{
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#ifdef CONFIG_USER_ONLY
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helper_retaddr = ra;
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#endif
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}
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/*
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* The result of tlb_vaddr_to_host for user-only is just g2h(x),
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* which is always non-null. Elide the useless test.
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@ -4143,7 +4136,6 @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
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return;
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}
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mem_off = reg_off >> diffsz;
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set_helper_retaddr(retaddr);
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/*
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* If the (remaining) load is entirely within a single page, then:
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@ -4158,7 +4150,6 @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
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if (test_host_page(host)) {
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mem_off = host_fn(vd, vg, host - mem_off, mem_off, mem_max);
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tcg_debug_assert(mem_off == mem_max);
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set_helper_retaddr(0);
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/* After having taken any fault, zero leading inactive elements. */
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swap_memzero(vd, reg_off);
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return;
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@ -4209,7 +4200,6 @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
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}
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#endif
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set_helper_retaddr(0);
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memcpy(vd, &scratch, reg_max);
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}
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@ -4269,7 +4259,6 @@ static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
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intptr_t i, oprsz = simd_oprsz(desc);
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ARMVectorReg scratch[2] = { };
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set_helper_retaddr(ra);
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for (i = 0; i < oprsz; ) {
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uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
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do {
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@ -4281,7 +4270,6 @@ static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
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addr += 2 * size;
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} while (i & 15);
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}
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set_helper_retaddr(0);
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/* Wait until all exceptions have been raised to write back. */
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memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
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@ -4296,7 +4284,6 @@ static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
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intptr_t i, oprsz = simd_oprsz(desc);
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ARMVectorReg scratch[3] = { };
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set_helper_retaddr(ra);
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for (i = 0; i < oprsz; ) {
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uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
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do {
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@ -4309,7 +4296,6 @@ static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
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addr += 3 * size;
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} while (i & 15);
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}
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set_helper_retaddr(0);
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/* Wait until all exceptions have been raised to write back. */
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memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
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@ -4325,7 +4311,6 @@ static void sve_ld4_r(CPUARMState *env, void *vg, target_ulong addr,
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intptr_t i, oprsz = simd_oprsz(desc);
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ARMVectorReg scratch[4] = { };
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set_helper_retaddr(ra);
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for (i = 0; i < oprsz; ) {
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uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
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do {
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@ -4339,7 +4324,6 @@ static void sve_ld4_r(CPUARMState *env, void *vg, target_ulong addr,
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addr += 4 * size;
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} while (i & 15);
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}
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set_helper_retaddr(0);
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/* Wait until all exceptions have been raised to write back. */
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memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz);
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@ -4446,7 +4430,6 @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
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return;
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}
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mem_off = reg_off >> diffsz;
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set_helper_retaddr(retaddr);
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/*
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* If the (remaining) load is entirely within a single page, then:
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@ -4461,7 +4444,6 @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
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if (test_host_page(host)) {
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mem_off = host_fn(vd, vg, host - mem_off, mem_off, mem_max);
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tcg_debug_assert(mem_off == mem_max);
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set_helper_retaddr(0);
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/* After any fault, zero any leading inactive elements. */
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swap_memzero(vd, reg_off);
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return;
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@ -4504,7 +4486,6 @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
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}
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#endif
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set_helper_retaddr(0);
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record_fault(env, reg_off, reg_max);
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}
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@ -4651,7 +4632,6 @@ static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
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intptr_t i, oprsz = simd_oprsz(desc);
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void *vd = &env->vfp.zregs[rd];
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set_helper_retaddr(ra);
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for (i = 0; i < oprsz; ) {
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uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
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do {
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@ -4662,7 +4642,6 @@ static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
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addr += msize;
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} while (i & 15);
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}
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set_helper_retaddr(0);
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}
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static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
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@ -4675,7 +4654,6 @@ static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
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void *d1 = &env->vfp.zregs[rd];
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void *d2 = &env->vfp.zregs[(rd + 1) & 31];
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set_helper_retaddr(ra);
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for (i = 0; i < oprsz; ) {
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uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
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do {
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@ -4687,7 +4665,6 @@ static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
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addr += 2 * msize;
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} while (i & 15);
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}
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set_helper_retaddr(0);
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}
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static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
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@ -4701,7 +4678,6 @@ static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
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void *d2 = &env->vfp.zregs[(rd + 1) & 31];
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void *d3 = &env->vfp.zregs[(rd + 2) & 31];
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set_helper_retaddr(ra);
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for (i = 0; i < oprsz; ) {
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uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
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do {
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@ -4714,7 +4690,6 @@ static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
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addr += 3 * msize;
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} while (i & 15);
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}
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set_helper_retaddr(0);
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}
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static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
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@ -4729,7 +4704,6 @@ static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
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void *d3 = &env->vfp.zregs[(rd + 2) & 31];
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void *d4 = &env->vfp.zregs[(rd + 3) & 31];
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set_helper_retaddr(ra);
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for (i = 0; i < oprsz; ) {
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uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
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do {
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@ -4743,7 +4717,6 @@ static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
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addr += 4 * msize;
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} while (i & 15);
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}
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set_helper_retaddr(0);
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}
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#define DO_STN_1(N, NAME, ESIZE) \
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@ -4839,7 +4812,6 @@ static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
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intptr_t i, oprsz = simd_oprsz(desc);
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ARMVectorReg scratch = { };
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set_helper_retaddr(ra);
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for (i = 0; i < oprsz; ) {
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uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
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do {
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@ -4850,7 +4822,6 @@ static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
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i += 4, pg >>= 4;
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} while (i & 15);
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}
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set_helper_retaddr(0);
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/* Wait until all exceptions have been raised to write back. */
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memcpy(vd, &scratch, oprsz);
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@ -4864,7 +4835,6 @@ static void sve_ld1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
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intptr_t i, oprsz = simd_oprsz(desc) / 8;
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ARMVectorReg scratch = { };
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set_helper_retaddr(ra);
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for (i = 0; i < oprsz; i++) {
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uint8_t pg = *(uint8_t *)(vg + H1(i));
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if (likely(pg & 1)) {
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@ -4872,7 +4842,6 @@ static void sve_ld1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
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tlb_fn(env, &scratch, i * 8, base + (off << scale), ra);
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}
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}
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set_helper_retaddr(0);
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/* Wait until all exceptions have been raised to write back. */
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memcpy(vd, &scratch, oprsz * 8);
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@ -5044,13 +5013,11 @@ static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
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reg_off = find_next_active(vg, 0, reg_max, MO_32);
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if (likely(reg_off < reg_max)) {
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/* Perform one normal read, which will fault or not. */
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set_helper_retaddr(ra);
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addr = off_fn(vm, reg_off);
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addr = base + (addr << scale);
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tlb_fn(env, vd, reg_off, addr, ra);
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/* The rest of the reads will be non-faulting. */
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set_helper_retaddr(0);
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}
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/* After any fault, zero the leading predicated false elements. */
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@ -5086,13 +5053,11 @@ static inline void sve_ldff1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
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reg_off = find_next_active(vg, 0, reg_max, MO_64);
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if (likely(reg_off < reg_max)) {
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/* Perform one normal read, which will fault or not. */
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set_helper_retaddr(ra);
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addr = off_fn(vm, reg_off);
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addr = base + (addr << scale);
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tlb_fn(env, vd, reg_off, addr, ra);
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/* The rest of the reads will be non-faulting. */
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set_helper_retaddr(0);
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}
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/* After any fault, zero the leading predicated false elements. */
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@ -5204,7 +5169,6 @@ static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
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const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
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intptr_t i, oprsz = simd_oprsz(desc);
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set_helper_retaddr(ra);
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for (i = 0; i < oprsz; ) {
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uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
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do {
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@ -5215,7 +5179,6 @@ static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
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i += 4, pg >>= 4;
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} while (i & 15);
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}
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set_helper_retaddr(0);
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}
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static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
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@ -5225,7 +5188,6 @@ static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
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const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
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intptr_t i, oprsz = simd_oprsz(desc) / 8;
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set_helper_retaddr(ra);
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for (i = 0; i < oprsz; i++) {
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uint8_t pg = *(uint8_t *)(vg + H1(i));
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if (likely(pg & 1)) {
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@ -5233,7 +5195,6 @@ static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
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tlb_fn(env, vd, i * 8, base + (off << scale), ra);
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}
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}
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set_helper_retaddr(0);
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}
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#define DO_ST1_ZPZ_S(MEM, OFS) \
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