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target-sparc: add UltraSPARC T1 TLB #defines

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Backports commit 5b5352b2f41e460f213a515e087c24dac1322f49 from qemu
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Artyom Tarasenko 2018-03-01 20:38:25 -05:00 committed by Lioncash
parent b3f7d376cc
commit f486053ae0
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1 changed files with 4 additions and 0 deletions
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qemu/target-sparc/cpu.h
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@ -332,6 +332,10 @@ enum {
#define TTE_PGSIZE_UA2005(tte) ((tte) & 7ULL)
#define TTE_PA(tte) ((tte) & 0x1ffffffe000ULL)
/* UltraSPARC T1 specific */
#define TLB_UST1_IS_REAL_BIT (1ULL << 9) /* Real translation entry */
#define TLB_UST1_IS_SUN4V_BIT (1ULL << 10) /* sun4u/sun4v TTE format switch */
#define SFSR_NF_BIT (1ULL << 24) /* JPS1 NoFault */
#define SFSR_TM_BIT (1ULL << 15) /* JPS1 TLB Miss */
#define SFSR_FT_VA_IMMU_BIT (1ULL << 13) /* USIIi VA out of range (IMMU) */