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target/arm: Implement SVE Bitwise Immediate Group

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Backports commit e1fa1164f397bbd381439ed32d97d9b4b4d7eb43 from qemu
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Richard Henderson 2018-05-20 05:17:49 -04:00 committed by Lioncash
parent 89038c1e4b
commit f4ecf1a152
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2 changed files with 67 additions and 0 deletions
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17
qemu/target/arm/sve.decode
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@ -49,6 +49,7 @@
&rr_esz rd rn esz &rr_esz rd rn esz
&rri rd rn imm &rri rd rn imm
&rr_dbm rd rn dbm
&rrri rd rn rm imm &rrri rd rn rm imm
&rri_esz rd rn imm esz &rri_esz rd rn imm esz
&rrr_esz rd rn rm esz &rrr_esz rd rn rm esz
@ -111,6 +112,10 @@
@rd_rn_tszimm ........ .. ... ... ...... rn:5 rd:5 \ @rd_rn_tszimm ........ .. ... ... ...... rn:5 rd:5 \
&rri_esz esz=%tszimm16_esz &rri_esz esz=%tszimm16_esz
# Two register operand, one encoded bitmask.
@rdn_dbm ........ .. .... dbm:13 rd:5 \
&rr_dbm rn=%reg_movprfx
# Basic Load/Store with 9-bit immediate offset # Basic Load/Store with 9-bit immediate offset
@pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \ @pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \
&rri imm=%imm9_16_10 &rri imm=%imm9_16_10
@ -330,6 +335,18 @@ INCDEC_v 00000100 .. 1 1 .... 1100 0 d:1 ..... ..... @incdec2_cnt u=1
# Note these require esz != 0. # Note these require esz != 0.
SINCDEC_v 00000100 .. 1 0 .... 1100 d:1 u:1 ..... ..... @incdec2_cnt SINCDEC_v 00000100 .. 1 0 .... 1100 d:1 u:1 ..... ..... @incdec2_cnt
### SVE Bitwise Immediate Group
# SVE bitwise logical with immediate (unpredicated)
ORR_zzi 00000101 00 0000 ............. ..... @rdn_dbm
EOR_zzi 00000101 01 0000 ............. ..... @rdn_dbm
AND_zzi 00000101 10 0000 ............. ..... @rdn_dbm
# SVE broadcast bitmask immediate
DUPM 00000101 11 0000 dbm:13 rd:5
### SVE Predicate Logical Operations Group
# SVE predicate logical operations # SVE predicate logical operations
AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s
BIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s BIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s

50
qemu/target/arm/translate-sve.c
View file

@ -1854,6 +1854,56 @@ static bool trans_SINCDEC_v(DisasContext *s, arg_incdec2_cnt *a,
return true; return true;
} }
/*
*** SVE Bitwise Immediate Group
*/
static bool do_zz_dbm(DisasContext *s, arg_rr_dbm *a, GVecGen2iFn *gvec_fn)
{
uint64_t imm;
if (!logic_imm_decode_wmask(&imm, extract32(a->dbm, 12, 1),
extract32(a->dbm, 0, 6),
extract32(a->dbm, 6, 6))) {
return false;
}
if (sve_access_check(s)) {
TCGContext *tcg_ctx = s->uc->tcg_ctx;
unsigned vsz = vec_full_reg_size(s);
gvec_fn(tcg_ctx, MO_64, vec_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn), imm, vsz, vsz);
}
return true;
}
static bool trans_AND_zzi(DisasContext *s, arg_rr_dbm *a, uint32_t insn)
{
return do_zz_dbm(s, a, tcg_gen_gvec_andi);
}
static bool trans_ORR_zzi(DisasContext *s, arg_rr_dbm *a, uint32_t insn)
{
return do_zz_dbm(s, a, tcg_gen_gvec_ori);
}
static bool trans_EOR_zzi(DisasContext *s, arg_rr_dbm *a, uint32_t insn)
{
return do_zz_dbm(s, a, tcg_gen_gvec_xori);
}
static bool trans_DUPM(DisasContext *s, arg_DUPM *a, uint32_t insn)
{
uint64_t imm;
if (!logic_imm_decode_wmask(&imm, extract32(a->dbm, 12, 1),
extract32(a->dbm, 0, 6),
extract32(a->dbm, 6, 6))) {
return false;
}
if (sve_access_check(s)) {
do_dupi_z(s, a->rd, imm);
}
return true;
}
/* /*
*** SVE Memory - 32-bit Gather and Unsized Contiguous Group *** SVE Memory - 32-bit Gather and Unsized Contiguous Group
*/ */