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tcg: Add tcg_gen_mulsu2_{i32,i64,tl}

Browse source 
This multiply has one signed input and one unsigned input,
producing the full double-width result.

Backports commit 5087abfb7dfd1d368ae6939420057036b4d8e509 from qemu
This commit is contained in:
Richard Henderson 2018-03-01 08:37:11 -05:00 committed by Lioncash
parent f9d91a81b5
commit f5a35908da
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
16 changed files with 75 additions and 0 deletions
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2
qemu/aarch64.h
View file

@ -3014,6 +3014,8 @@
#define tcg_gen_muli_i64 tcg_gen_muli_i64_aarch64
#define tcg_gen_muls2_i32 tcg_gen_muls2_i32_aarch64
#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_aarch64
#define tcg_gen_mulsu2_i32 tcg_gen_mulsu2_i32_aarch64
#define tcg_gen_mulsu2_i64 tcg_gen_mulsu2_i64_aarch64
#define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_aarch64
#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_aarch64
#define tcg_gen_nand_i32 tcg_gen_nand_i32_aarch64

2
qemu/aarch64eb.h
View file

@ -3014,6 +3014,8 @@
#define tcg_gen_muli_i64 tcg_gen_muli_i64_aarch64eb
#define tcg_gen_muls2_i32 tcg_gen_muls2_i32_aarch64eb
#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_aarch64eb
#define tcg_gen_mulsu2_i32 tcg_gen_mulsu2_i32_aarch64eb
#define tcg_gen_mulsu2_i64 tcg_gen_mulsu2_i64_aarch64eb
#define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_aarch64eb
#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_aarch64eb
#define tcg_gen_nand_i32 tcg_gen_nand_i32_aarch64eb

2
qemu/arm.h
View file

@ -3014,6 +3014,8 @@
#define tcg_gen_muli_i64 tcg_gen_muli_i64_arm
#define tcg_gen_muls2_i32 tcg_gen_muls2_i32_arm
#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_arm
#define tcg_gen_mulsu2_i32 tcg_gen_mulsu2_i32_arm
#define tcg_gen_mulsu2_i64 tcg_gen_mulsu2_i64_arm
#define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_arm
#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_arm
#define tcg_gen_nand_i32 tcg_gen_nand_i32_arm

2
qemu/armeb.h
View file

@ -3014,6 +3014,8 @@
#define tcg_gen_muli_i64 tcg_gen_muli_i64_armeb
#define tcg_gen_muls2_i32 tcg_gen_muls2_i32_armeb
#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_armeb
#define tcg_gen_mulsu2_i32 tcg_gen_mulsu2_i32_armeb
#define tcg_gen_mulsu2_i64 tcg_gen_mulsu2_i64_armeb
#define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_armeb
#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_armeb
#define tcg_gen_nand_i32 tcg_gen_nand_i32_armeb

2
qemu/header_gen.py
View file

@ -3020,6 +3020,8 @@ symbols = (
'tcg_gen_muli_i64',
'tcg_gen_muls2_i32',
'tcg_gen_muls2_i64',
'tcg_gen_mulsu2_i32',
'tcg_gen_mulsu2_i64',
'tcg_gen_mulu2_i32',
'tcg_gen_mulu2_i64',
'tcg_gen_nand_i32',

2
qemu/m68k.h
View file

@ -3014,6 +3014,8 @@
#define tcg_gen_muli_i64 tcg_gen_muli_i64_m68k
#define tcg_gen_muls2_i32 tcg_gen_muls2_i32_m68k
#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_m68k
#define tcg_gen_mulsu2_i32 tcg_gen_mulsu2_i32_m68k
#define tcg_gen_mulsu2_i64 tcg_gen_mulsu2_i64_m68k
#define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_m68k
#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_m68k
#define tcg_gen_nand_i32 tcg_gen_nand_i32_m68k

2
qemu/mips.h
View file

@ -3014,6 +3014,8 @@
#define tcg_gen_muli_i64 tcg_gen_muli_i64_mips
#define tcg_gen_muls2_i32 tcg_gen_muls2_i32_mips
#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_mips
#define tcg_gen_mulsu2_i32 tcg_gen_mulsu2_i32_mips
#define tcg_gen_mulsu2_i64 tcg_gen_mulsu2_i64_mips
#define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_mips
#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_mips
#define tcg_gen_nand_i32 tcg_gen_nand_i32_mips

2
qemu/mips64.h
View file

@ -3014,6 +3014,8 @@
#define tcg_gen_muli_i64 tcg_gen_muli_i64_mips64
#define tcg_gen_muls2_i32 tcg_gen_muls2_i32_mips64
#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_mips64
#define tcg_gen_mulsu2_i32 tcg_gen_mulsu2_i32_mips64
#define tcg_gen_mulsu2_i64 tcg_gen_mulsu2_i64_mips64
#define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_mips64
#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_mips64
#define tcg_gen_nand_i32 tcg_gen_nand_i32_mips64

2
qemu/mips64el.h
View file

@ -3014,6 +3014,8 @@
#define tcg_gen_muli_i64 tcg_gen_muli_i64_mips64el
#define tcg_gen_muls2_i32 tcg_gen_muls2_i32_mips64el
#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_mips64el
#define tcg_gen_mulsu2_i32 tcg_gen_mulsu2_i32_mips64el
#define tcg_gen_mulsu2_i64 tcg_gen_mulsu2_i64_mips64el
#define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_mips64el
#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_mips64el
#define tcg_gen_nand_i32 tcg_gen_nand_i32_mips64el

2
qemu/mipsel.h
View file

@ -3014,6 +3014,8 @@
#define tcg_gen_muli_i64 tcg_gen_muli_i64_mipsel
#define tcg_gen_muls2_i32 tcg_gen_muls2_i32_mipsel
#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_mipsel
#define tcg_gen_mulsu2_i32 tcg_gen_mulsu2_i32_mipsel
#define tcg_gen_mulsu2_i64 tcg_gen_mulsu2_i64_mipsel
#define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_mipsel
#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_mipsel
#define tcg_gen_nand_i32 tcg_gen_nand_i32_mipsel

2
qemu/powerpc.h
View file

@ -3014,6 +3014,8 @@
#define tcg_gen_muli_i64 tcg_gen_muli_i64_powerpc
#define tcg_gen_muls2_i32 tcg_gen_muls2_i32_powerpc
#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_powerpc
#define tcg_gen_mulsu2_i32 tcg_gen_mulsu2_i32_powerpc
#define tcg_gen_mulsu2_i64 tcg_gen_mulsu2_i64_powerpc
#define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_powerpc
#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_powerpc
#define tcg_gen_nand_i32 tcg_gen_nand_i32_powerpc

2
qemu/sparc.h
View file

@ -3014,6 +3014,8 @@
#define tcg_gen_muli_i64 tcg_gen_muli_i64_sparc
#define tcg_gen_muls2_i32 tcg_gen_muls2_i32_sparc
#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_sparc
#define tcg_gen_mulsu2_i32 tcg_gen_mulsu2_i32_sparc
#define tcg_gen_mulsu2_i64 tcg_gen_mulsu2_i64_sparc
#define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_sparc
#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_sparc
#define tcg_gen_nand_i32 tcg_gen_nand_i32_sparc

2
qemu/sparc64.h
View file

@ -3014,6 +3014,8 @@
#define tcg_gen_muli_i64 tcg_gen_muli_i64_sparc64
#define tcg_gen_muls2_i32 tcg_gen_muls2_i32_sparc64
#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_sparc64
#define tcg_gen_mulsu2_i32 tcg_gen_mulsu2_i32_sparc64
#define tcg_gen_mulsu2_i64 tcg_gen_mulsu2_i64_sparc64
#define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_sparc64
#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_sparc64
#define tcg_gen_nand_i32 tcg_gen_nand_i32_sparc64

43
qemu/tcg/tcg-op.c
View file

@ -677,6 +677,33 @@ void tcg_gen_muls2_i32(TCGContext *s, TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, T
}
}
void tcg_gen_mulsu2_i32(TCGContext *s, TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2)
{
if (TCG_TARGET_REG_BITS == 32) {
TCGv_i32 t0 = tcg_temp_new_i32(s);
TCGv_i32 t1 = tcg_temp_new_i32(s);
TCGv_i32 t2 = tcg_temp_new_i32(s);
tcg_gen_mulu2_i32(s, t0, t1, arg1, arg2);
/* Adjust for negative input for the signed arg1. */
tcg_gen_sari_i32(s, t2, arg1, 31);
tcg_gen_and_i32(s, t2, t2, arg2);
tcg_gen_sub_i32(s, rh, t1, t2);
tcg_gen_mov_i32(s, rl, t0);
tcg_temp_free_i32(s, t0);
tcg_temp_free_i32(s, t1);
tcg_temp_free_i32(s, t2);
} else {
TCGv_i64 t0 = tcg_temp_new_i64(s);
TCGv_i64 t1 = tcg_temp_new_i64(s);
tcg_gen_ext_i32_i64(s, t0, arg1);
tcg_gen_extu_i32_i64(s, t1, arg2);
tcg_gen_mul_i64(s, t0, t0, t1);
tcg_gen_extr_i64_i32(s, rl, rh, t0);
tcg_temp_free_i64(s, t0);
tcg_temp_free_i64(s, t1);
}
}
void tcg_gen_ext8s_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg)
{
if (TCG_TARGET_HAS_ext8s_i32) {
@ -1747,6 +1774,22 @@ void tcg_gen_muls2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, T
}
}
void tcg_gen_mulsu2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2)
{
TCGv_i64 t0 = tcg_temp_new_i64(s);
TCGv_i64 t1 = tcg_temp_new_i64(s);
TCGv_i64 t2 = tcg_temp_new_i64(s);
tcg_gen_mulu2_i64(s, t0, t1, arg1, arg2);
/* Adjust for negative input for the signed arg1. */
tcg_gen_sari_i64(s, t2, arg1, 63);
tcg_gen_and_i64(s, t2, t2, arg2);
tcg_gen_sub_i64(s, rh, t1, t2);
tcg_gen_mov_i64(s, rl, t0);
tcg_temp_free_i64(s, t0);
tcg_temp_free_i64(s, t1);
tcg_temp_free_i64(s, t2);
}
/* Size changing operations. */
void tcg_gen_extrl_i64_i32(TCGContext *s, TCGv_i32 ret, TCGv_i64 arg)

4
qemu/tcg/tcg-op.h
View file

@ -314,6 +314,7 @@ void tcg_gen_sub2_i32(TCGContext *s, TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh);
void tcg_gen_mulu2_i32(TCGContext *s, TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
void tcg_gen_muls2_i32(TCGContext *s, TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
void tcg_gen_mulsu2_i32(TCGContext *s, TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
void tcg_gen_ext8s_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg);
void tcg_gen_ext16s_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg);
void tcg_gen_ext8u_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg);
@ -482,6 +483,7 @@ void tcg_gen_sub2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
void tcg_gen_mulu2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
void tcg_gen_muls2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
void tcg_gen_mulsu2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
void tcg_gen_not_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg);
void tcg_gen_ext8s_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg);
void tcg_gen_ext16s_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg);
@ -958,6 +960,7 @@ void tcg_gen_atomic_xor_fetch_i64(TCGContext *, TCGv_i64, TCGv, TCGv_i64, TCGArg
#define tcg_gen_sub2_tl tcg_gen_sub2_i64
#define tcg_gen_mulu2_tl tcg_gen_mulu2_i64
#define tcg_gen_muls2_tl tcg_gen_muls2_i64
#define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i64
#define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i64
#define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i64
#define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i64
@ -1045,6 +1048,7 @@ void tcg_gen_atomic_xor_fetch_i64(TCGContext *, TCGv_i64, TCGv, TCGv_i64, TCGArg
#define tcg_gen_sub2_tl tcg_gen_sub2_i32
#define tcg_gen_mulu2_tl tcg_gen_mulu2_i32
#define tcg_gen_muls2_tl tcg_gen_muls2_i32
#define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i32
#define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i32
#define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i32
#define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i32

2
qemu/x86_64.h
View file

@ -3014,6 +3014,8 @@
#define tcg_gen_muli_i64 tcg_gen_muli_i64_x86_64
#define tcg_gen_muls2_i32 tcg_gen_muls2_i32_x86_64
#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_x86_64
#define tcg_gen_mulsu2_i32 tcg_gen_mulsu2_i32_x86_64
#define tcg_gen_mulsu2_i64 tcg_gen_mulsu2_i64_x86_64
#define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_x86_64
#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_x86_64
#define tcg_gen_nand_i32 tcg_gen_nand_i32_x86_64