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target-arm: Suppress TBI for S2 translations

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Stage-2 MMU translations do not have configurable TBI as
the top byte is always 0 (48-bit IPAs).

Backports commit 1edee4708a0e3163cbf20fac325be456abd960bb from qemu
This commit is contained in:
Edgar E. Iglesias 2018-02-15 12:33:38 -05:00 committed by Lioncash
parent 097325acd6
commit f5b3b9f6e9
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 3 additions and 1 deletions
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qemu/target-arm/helper.c
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@ -5743,7 +5743,9 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
if (arm_el_is_aa64(env, el)) { if (arm_el_is_aa64(env, el)) {
va_size = 64; va_size = 64;
if (el > 1) { if (el > 1) {
if (mmu_idx != ARMMMUIdx_S2NS) {
tbi = extract64(tcr->raw_tcr, 20, 1); tbi = extract64(tcr->raw_tcr, 20, 1);
}
} else { } else {
if (extract64(address, 55, 1)) { if (extract64(address, 55, 1)) {
tbi = extract64(tcr->raw_tcr, 38, 1); tbi = extract64(tcr->raw_tcr, 38, 1);