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target-i386: Add Intel SHA_NI instruction support.

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Add SHA_NI feature bit. Its spec can be found at:
https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf

Backports commit 638cbd452d3a92a2ab18caee73078483d90f64eb from qemu
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Yi Sun 2018-03-01 10:52:22 -05:00 committed by Lioncash
parent 81ad780e5e
commit f6e624d97b
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2 changed files with 2 additions and 1 deletions
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2
qemu/target-i386/cpu.c
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@ -300,7 +300,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
"avx512f", "avx512dq", "rdseed", "adx",
"smap", "avx512ifma", "pcommit", "clflushopt",
"clwb", NULL, "avx512pf", "avx512er",
"avx512cd", NULL, "avx512bw", "avx512vl",
"avx512cd", "sha-ni", "avx512bw", "avx512vl",
},
7,
true, 0,

1
qemu/target-i386/cpu.h
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@ -619,6 +619,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */
#define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */
#define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */
#define CPUID_7_0_EBX_SHA_NI (1U << 29) /* SHA1/SHA256 Instruction Extensions */
#define CPUID_7_0_EBX_AVX512BW (1U << 30) /* AVX-512 Byte and Word Instructions */
#define CPUID_7_0_EBX_AVX512VL (1U << 31) /* AVX-512 Vector Length Extensions */