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target/arm: Implement v8.3-RCPC
The v8.3-RCPC extension implements three new load instructions which provide slightly weaker consistency guarantees than the existing load-acquire operations. For QEMU we choose to simply implement them with a full LDAQ barrier. Backports commit 2677cf9f92a5319bb995927f9225940414ce879d from qemu
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@ -3647,6 +3647,11 @@ static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id)
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FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
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}
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static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0;
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}
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/*
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* Feature tests for "does this exist in either 32-bit or 64-bit?"
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*/
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@ -298,6 +298,7 @@ static void aarch64_max_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
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t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
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t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
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t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 1); /* ARMv8.3-RCPC */
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cpu->isar.id_aa64isar1 = t;
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t = cpu->isar.id_aa64pfr0;
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@ -3335,6 +3335,8 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
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int rs = extract32(insn, 16, 5);
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int rn = extract32(insn, 5, 5);
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int o3_opc = extract32(insn, 12, 4);
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bool r = extract32(insn, 22, 1);
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bool a = extract32(insn, 23, 1);
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TCGv_i64 tcg_rs, clean_addr;
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AtomicThreeOpFn *fn;
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@ -3370,6 +3372,13 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
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case 010: /* SWP */
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fn = tcg_gen_atomic_xchg_i64;
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break;
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case 014: /* LDAPR, LDAPRH, LDAPRB */
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if (!dc_isar_feature(aa64_rcpc_8_3, s) ||
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rs != 31 || a != 1 || r != 0) {
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unallocated_encoding(s);
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return;
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}
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break;
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default:
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unallocated_encoding(s);
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return;
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@ -3379,6 +3388,22 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
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gen_check_sp_alignment(s);
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}
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clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn));
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if (o3_opc == 014) {
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/*
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* LDAPR* are a special case because they are a simple load, not a
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* fetch-and-do-something op.
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* The architectural consistency requirements here are weaker than
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* full load-acquire (we only need "load-acquire processor consistent"),
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* but we choose to implement them as full LDAQ.
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*/
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do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false,
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true, rt, disas_ldst_compute_iss_sf(size, false, 0), true);
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tcg_gen_mb(tcg_ctx, TCG_MO_ALL | TCG_BAR_LDAQ);
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return;
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}
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tcg_rs = read_cpu_reg(s, rs, true);
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if (o3_opc == 1) { /* LDCLR */
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