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target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate

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cpsr has been treated as being the same as spsr, but it isn't.
Since PSTATE_SS isn't in cpsr, remove it and move it into env->pstate.

This allows us to add support for CPSR_DIT, adding helper functions
to merge SPSR_ELx to and from CPSR.

Backports f944a854ce4007000accf7c191b5b52916947198
This commit is contained in:
Rebecca Cran 2021-03-04 18:24:16 -05:00 committed by Lioncash
parent d8458f14af
commit f7424d89e2
3 changed files with 40 additions and 13 deletions
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27
qemu/target/arm/helper-a64.c
View file

@ -943,11 +943,31 @@ static int el_from_spsr(uint32_t spsr)
}
}
static void cpsr_write_from_spsr_elx(CPUARMState *env,
uint32_t val)
{
uint32_t mask;
/* Save SPSR_ELx.SS into PSTATE. */
env->pstate = (env->pstate & ~PSTATE_SS) | (val & PSTATE_SS);
val &= ~PSTATE_SS;
/* Move DIT to the correct location for CPSR */
if (val & PSTATE_DIT) {
val &= ~PSTATE_DIT;
val |= CPSR_DIT;
}
mask = aarch32_cpsr_valid_mask(env->features, \
&env_archcpu(env)->isar);
cpsr_write(env, val, mask, CPSRWriteRaw);
}
void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
{
int cur_el = arm_current_el(env);
unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el);
uint32_t mask, spsr = env->banked_spsr[spsr_idx];
uint32_t spsr = env->banked_spsr[spsr_idx];
int new_el;
bool return_to_aa64 = (spsr & PSTATE_nRW) == 0;
@ -997,10 +1017,9 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
* will sort the register banks out for us, and we've already
* caught all the bad-mode cases in el_from_spsr().
*/
mask = aarch32_cpsr_valid_mask(env->features, &env_archcpu(env)->isar);
cpsr_write(env, spsr, mask, CPSRWriteRaw);
cpsr_write_from_spsr_elx(env, spsr);
if (!arm_singlestep_active(env)) {
env->uncached_cpsr &= ~PSTATE_SS;
env->pstate &= ~PSTATE_SS;
}
aarch64_sync_64_to_32(env);

17
qemu/target/arm/helper.c
View file

@ -9091,7 +9091,7 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode,
* For exceptions taken to AArch32 we must clear the SS bit in both
* PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
*/
env->uncached_cpsr &= ~PSTATE_SS;
env->pstate &= ~PSTATE_SS;
env->spsr = cpsr_read(env);
/* Clear IT bits. */
env->condexec_bits = 0;
@ -9447,6 +9447,21 @@ static int aarch64_regnum(CPUARMState *env, int aarch32_reg)
}
}
static uint32_t cpsr_read_for_spsr_elx(CPUARMState *env)
{
uint32_t ret = cpsr_read(env);
/* Move DIT to the correct location for SPSR_ELx */
if (ret & CPSR_DIT) {
ret &= ~CPSR_DIT;
ret |= PSTATE_DIT;
}
/* Merge PSTATE.SS into SPSR_ELx */
ret |= env->pstate & PSTATE_SS;
return ret;
}
/* Handle exception entry to a target EL which is using AArch64 */
// Unicorn: underscore appended to prevent silly clashing with defines
static void arm_cpu_do_interrupt_aarch64_(CPUState *cs)

9
qemu/target/arm/op_helper.c
View file

@ -397,14 +397,7 @@ void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome)
uint32_t HELPER(cpsr_read)(CPUARMState *env)
{
/*
* We store the ARMv8 PSTATE.SS bit in env->uncached_cpsr.
* This is convenient for populating SPSR_ELx, but must be
* hidden from aarch32 mode, where it is not visible.
*
* TODO: ARMv8.4-DIT -- need to move SS somewhere else.
*/
return cpsr_read(env) & ~(CPSR_EXEC | PSTATE_SS);
return cpsr_read(env) & ~CPSR_EXEC;
}
void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)