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target-arm: Add S2 translation to 32bit S1 PTWs

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Add support for applying S2 translation to 32bit S1
page-table walks.

Backports commit a614e69854a2e601716ee44dfe15c09b8b88f620 from qemu
This commit is contained in:
Edgar E. Iglesias 2018-02-17 13:40:28 -05:00 committed by Lioncash
parent 085a94faac
commit f779375656
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 17 additions and 5 deletions
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22
qemu/target-arm/helper.c
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@ -5597,11 +5597,19 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
* was being done for a CPU load/store or an address translation instruction * was being done for a CPU load/store or an address translation instruction
* (but not if it was for a debug access). * (but not if it was for a debug access).
*/ */
static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure) static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
ARMMMUIdx mmu_idx, uint32_t *fsr,
ARMMMUFaultInfo *fi)
{ {
ARMCPU *cpu = ARM_CPU(cs->uc, cs);
CPUARMState *env = &cpu->env;
MemTxAttrs attrs = {0}; MemTxAttrs attrs = {0};
attrs.secure = is_secure; attrs.secure = is_secure;
addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi);
if (fi->s1ptw) {
return 0;
}
return address_space_ldl(cs->as, addr, attrs, NULL); return address_space_ldl(cs->as, addr, attrs, NULL);
} }
@ -5645,7 +5653,8 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
code = 5; code = 5;
goto do_fault; goto do_fault;
} }
desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx)); desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
mmu_idx, fsr, fi);
type = (desc & 3); type = (desc & 3);
domain = (desc >> 5) & 0x0f; domain = (desc >> 5) & 0x0f;
if (regime_el(env, mmu_idx) == 1) { if (regime_el(env, mmu_idx) == 1) {
@ -5681,7 +5690,8 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
/* Fine pagetable. */ /* Fine pagetable. */
table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
} }
desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx)); desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
mmu_idx, fsr, fi);
switch (desc & 3) { switch (desc & 3) {
case 0: /* Page translation fault. */ case 0: /* Page translation fault. */
code = 7; code = 7;
@ -5762,7 +5772,8 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
code = 5; code = 5;
goto do_fault; goto do_fault;
} }
desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx)); desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
mmu_idx, fsr, fi);
type = (desc & 3); type = (desc & 3);
if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) { if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
/* Section translation fault, or attempt to use the encoding /* Section translation fault, or attempt to use the encoding
@ -5813,7 +5824,8 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
ns = extract32(desc, 3, 1); ns = extract32(desc, 3, 1);
/* Lookup l2 entry. */ /* Lookup l2 entry. */
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx)); desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
mmu_idx, fsr, fi);
ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
switch (desc & 3) { switch (desc & 3) {
case 0: /* Page translation fault. */ case 0: /* Page translation fault. */