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target/arm: Adjust FPCR_MASK for FZ16

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When support for FZ16 was added, we failed to include the bit
within FPCR_MASK, which means that it could never be set.
Continue to zero FZ16 when ARMv8.2-FP16 is not enabled.

Fixes: d81ce0ef2c4

Backports commit 0b62159be33d45d00dfa34a317c6d3da30ffb480 from qemu
This commit is contained in:
Richard Henderson 2018-08-17 14:02:45 -04:00 committed by Lioncash
parent d2f3a6c0d5
commit f787dd15fd
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 6 additions and 1 deletions
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2
qemu/target/arm/cpu.h
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@ -1209,7 +1209,7 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val);
* we store the underlying state in fpscr and just mask on read/write.
*/
#define FPSR_MASK 0xf800009f
#define FPCR_MASK 0x07f79f00
#define FPCR_MASK 0x07ff9f00
#define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */
#define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */

5
qemu/target/arm/helper.c
View file

@ -10591,6 +10591,11 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
int i;
uint32_t changed;
/* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
if (!arm_feature(env, ARM_FEATURE_V8_FP16)) {
val &= ~FPCR_FZ16;
}
changed = env->vfp.xregs[ARM_VFP_FPSCR];
env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
env->vfp.vec_len = (val >> 16) & 7;