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target/arm: Implement Cortex-M55 model

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Now that we have implemented all the features needed by the v8.1M
architecture, we can add the model of the Cortex-M55. This is the
configuration without MVE support; we'll add MVE later

Backports 590e05d6b48937f6d3c631354fd706f8e005b8f6
This commit is contained in:
Peter Maydell 2021-03-03 20:06:04 -05:00 committed by Lioncash
parent e586a27a7b
commit f7939926dc
1 changed files with 43 additions and 0 deletions
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43
qemu/target/arm/cpu.c
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@ -1463,6 +1463,46 @@ static void cortex_m33_initfn(struct uc_struct *uc, Object *obj, void *opaque)
cpu->ctr = 0x8000c000; cpu->ctr = 0x8000c000;
} }
static void cortex_m55_initfn(struct uc_struct *uc, Object *obj, void *opaque)
{
ARMCPU *cpu = ARM_CPU(uc, obj);
set_feature(&cpu->env, ARM_FEATURE_V8);
set_feature(&cpu->env, ARM_FEATURE_V8_1M);
set_feature(&cpu->env, ARM_FEATURE_M);
set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
cpu->midr = 0x410fd221; /* r0p1 */
cpu->revidr = 0;
cpu->pmsav7_dregion = 16;
cpu->sau_sregion = 8;
/*
* These are the MVFR* values for the FPU, no MVE configuration;
* we will update them later when we implement MVE
*/
cpu->isar.mvfr0 = 0x10110221;
cpu->isar.mvfr1 = 0x12100011;
cpu->isar.mvfr2 = 0x00000040;
cpu->isar.id_pfr0 = 0x20000030;
cpu->isar.id_pfr1 = 0x00000230;
cpu->isar.id_dfr0 = 0x10200000;
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00111040;
cpu->isar.id_mmfr1 = 0x00000000;
cpu->isar.id_mmfr2 = 0x01000000;
cpu->isar.id_mmfr3 = 0x00000011;
cpu->isar.id_isar0 = 0x01103110;
cpu->isar.id_isar1 = 0x02212000;
cpu->isar.id_isar2 = 0x20232232;
cpu->isar.id_isar3 = 0x01111131;
cpu->isar.id_isar4 = 0x01310132;
cpu->isar.id_isar5 = 0x00000000;
cpu->isar.id_isar6 = 0x00000000;
cpu->clidr = 0x00000000; /* caches not implemented */
cpu->ctr = 0x8303c003;
}
static void arm_v7m_class_init(struct uc_struct *uc, ObjectClass *oc, void *data) static void arm_v7m_class_init(struct uc_struct *uc, ObjectClass *oc, void *data)
{ {
CPUClass *cc = CPU_CLASS(uc, oc); CPUClass *cc = CPU_CLASS(uc, oc);
@ -1474,6 +1514,7 @@ static void arm_v7m_class_init(struct uc_struct *uc, ObjectClass *oc, void *data
cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
} }
static const ARMCPRegInfo cortexr5_cp_reginfo[] = { static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
/* Dummy the TCM region regs for the moment */ /* Dummy the TCM region regs for the moment */
{ .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
@ -2006,6 +2047,8 @@ static const ARMCPUInfo arm_cpus[] = {
.class_init = arm_v7m_class_init }, .class_init = arm_v7m_class_init },
{ .name = "cortex-m33", .initfn = cortex_m33_initfn, { .name = "cortex-m33", .initfn = cortex_m33_initfn,
.class_init = arm_v7m_class_init }, .class_init = arm_v7m_class_init },
{ .name = "cortex-m55", .initfn = cortex_m55_initfn,
.class_init = arm_v7m_class_init },
{ .name = "cortex-r5", .initfn = cortex_r5_initfn }, { .name = "cortex-r5", .initfn = cortex_r5_initfn },
{ .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
{ .name = "cortex-a7", .initfn = cortex_a7_initfn }, { .name = "cortex-a7", .initfn = cortex_a7_initfn },