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target/arm: Implement SVE FP Compare with Zero Group

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Backports commit 4d2e2a03384a43c641e0cbca7ac79d7d0c50f666 from qemu
This commit is contained in:
Richard Henderson 2018-07-03 03:49:49 -04:00 committed by Lioncash
parent 942f3c835e
commit f7e0c9e079
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GPG key ID: 4E3C3CC1031BA9C7
7 changed files with 193 additions and 0 deletions
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18
qemu/aarch64.h
View file

@ -3534,15 +3534,33 @@
#define helper_sve_fcmeq_d helper_sve_fcmeq_d_aarch64
#define helper_sve_fcmeq_h helper_sve_fcmeq_h_aarch64
#define helper_sve_fcmeq_s helper_sve_fcmeq_s_aarch64
#define helper_sve_fcmeq0_d helper_sve_fcmeq0_d_aarch64
#define helper_sve_fcmeq0_h helper_sve_fcmeq0_h_aarch64
#define helper_sve_fcmeq0_s helper_sve_fcmeq0_s_aarch64
#define helper_sve_fcmge_d helper_sve_fcmge_d_aarch64
#define helper_sve_fcmge_h helper_sve_fcmge_h_aarch64
#define helper_sve_fcmge_s helper_sve_fcmge_s_aarch64
#define helper_sve_fcmge0_d helper_sve_fcmge0_d_aarch64
#define helper_sve_fcmge0_h helper_sve_fcmge0_h_aarch64
#define helper_sve_fcmge0_s helper_sve_fcmge0_s_aarch64
#define helper_sve_fcmgt_d helper_sve_fcmgt_d_aarch64
#define helper_sve_fcmgt_h helper_sve_fcmgt_h_aarch64
#define helper_sve_fcmgt_s helper_sve_fcmgt_s_aarch64
#define helper_sve_fcmgt0_d helper_sve_fcmgt0_d_aarch64
#define helper_sve_fcmgt0_h helper_sve_fcmgt0_h_aarch64
#define helper_sve_fcmgt0_s helper_sve_fcmgt0_s_aarch64
#define helper_sve_fcmle0_d helper_sve_fcmle0_d_aarch64
#define helper_sve_fcmle0_h helper_sve_fcmle0_h_aarch64
#define helper_sve_fcmle0_s helper_sve_fcmle0_s_aarch64
#define helper_sve_fcmlt0_d helper_sve_fcmlt0_d_aarch64
#define helper_sve_fcmlt0_h helper_sve_fcmlt0_h_aarch64
#define helper_sve_fcmlt0_s helper_sve_fcmlt0_s_aarch64
#define helper_sve_fcmne_d helper_sve_fcmne_d_aarch64
#define helper_sve_fcmne_h helper_sve_fcmne_h_aarch64
#define helper_sve_fcmne_s helper_sve_fcmne_s_aarch64
#define helper_sve_fcmne0_d helper_sve_fcmne0_d_aarch64
#define helper_sve_fcmne0_h helper_sve_fcmne0_h_aarch64
#define helper_sve_fcmne0_s helper_sve_fcmne0_s_aarch64
#define helper_sve_fcmuo_d helper_sve_fcmuo_d_aarch64
#define helper_sve_fcmuo_h helper_sve_fcmuo_h_aarch64
#define helper_sve_fcmuo_s helper_sve_fcmuo_s_aarch64

18
qemu/aarch64eb.h
View file

@ -3534,15 +3534,33 @@
#define helper_sve_fcmeq_d helper_sve_fcmeq_d_aarch64eb
#define helper_sve_fcmeq_h helper_sve_fcmeq_h_aarch64eb
#define helper_sve_fcmeq_s helper_sve_fcmeq_s_aarch64eb
#define helper_sve_fcmeq0_d helper_sve_fcmeq0_d_aarch64eb
#define helper_sve_fcmeq0_h helper_sve_fcmeq0_h_aarch64eb
#define helper_sve_fcmeq0_s helper_sve_fcmeq0_s_aarch64eb
#define helper_sve_fcmge_d helper_sve_fcmge_d_aarch64eb
#define helper_sve_fcmge_h helper_sve_fcmge_h_aarch64eb
#define helper_sve_fcmge_s helper_sve_fcmge_s_aarch64eb
#define helper_sve_fcmge0_d helper_sve_fcmge0_d_aarch64eb
#define helper_sve_fcmge0_h helper_sve_fcmge0_h_aarch64eb
#define helper_sve_fcmge0_s helper_sve_fcmge0_s_aarch64eb
#define helper_sve_fcmgt_d helper_sve_fcmgt_d_aarch64eb
#define helper_sve_fcmgt_h helper_sve_fcmgt_h_aarch64eb
#define helper_sve_fcmgt_s helper_sve_fcmgt_s_aarch64eb
#define helper_sve_fcmgt0_d helper_sve_fcmgt0_d_aarch64eb
#define helper_sve_fcmgt0_h helper_sve_fcmgt0_h_aarch64eb
#define helper_sve_fcmgt0_s helper_sve_fcmgt0_s_aarch64eb
#define helper_sve_fcmle0_d helper_sve_fcmle0_d_aarch64eb
#define helper_sve_fcmle0_h helper_sve_fcmle0_h_aarch64eb
#define helper_sve_fcmle0_s helper_sve_fcmle0_s_aarch64eb
#define helper_sve_fcmlt0_d helper_sve_fcmlt0_d_aarch64eb
#define helper_sve_fcmlt0_h helper_sve_fcmlt0_h_aarch64eb
#define helper_sve_fcmlt0_s helper_sve_fcmlt0_s_aarch64eb
#define helper_sve_fcmne_d helper_sve_fcmne_d_aarch64eb
#define helper_sve_fcmne_h helper_sve_fcmne_h_aarch64eb
#define helper_sve_fcmne_s helper_sve_fcmne_s_aarch64eb
#define helper_sve_fcmne0_d helper_sve_fcmne0_d_aarch64eb
#define helper_sve_fcmne0_h helper_sve_fcmne0_h_aarch64eb
#define helper_sve_fcmne0_s helper_sve_fcmne0_s_aarch64eb
#define helper_sve_fcmuo_d helper_sve_fcmuo_d_aarch64eb
#define helper_sve_fcmuo_h helper_sve_fcmuo_h_aarch64eb
#define helper_sve_fcmuo_s helper_sve_fcmuo_s_aarch64eb

18
qemu/header_gen.py
View file

@ -3555,15 +3555,33 @@ aarch64_symbols = (
'helper_sve_fcmeq_d',
'helper_sve_fcmeq_h',
'helper_sve_fcmeq_s',
'helper_sve_fcmeq0_d',
'helper_sve_fcmeq0_h',
'helper_sve_fcmeq0_s',
'helper_sve_fcmge_d',
'helper_sve_fcmge_h',
'helper_sve_fcmge_s',
'helper_sve_fcmge0_d',
'helper_sve_fcmge0_h',
'helper_sve_fcmge0_s',
'helper_sve_fcmgt_d',
'helper_sve_fcmgt_h',
'helper_sve_fcmgt_s',
'helper_sve_fcmgt0_d',
'helper_sve_fcmgt0_h',
'helper_sve_fcmgt0_s',
'helper_sve_fcmle0_d',
'helper_sve_fcmle0_h',
'helper_sve_fcmle0_s',
'helper_sve_fcmlt0_d',
'helper_sve_fcmlt0_h',
'helper_sve_fcmlt0_s',
'helper_sve_fcmne_d',
'helper_sve_fcmne_h',
'helper_sve_fcmne_s',
'helper_sve_fcmne0_d',
'helper_sve_fcmne0_h',
'helper_sve_fcmne0_s',
'helper_sve_fcmuo_d',
'helper_sve_fcmuo_h',
'helper_sve_fcmuo_s',

42
qemu/target/arm/helper-sve.h
View file

@ -767,6 +767,48 @@ DEF_HELPER_FLAGS_5(sve_fadda_s, TCG_CALL_NO_RWG,
DEF_HELPER_FLAGS_5(sve_fadda_d, TCG_CALL_NO_RWG,
i64, i64, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_fcmge0_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_fcmge0_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_fcmge0_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_fcmgt0_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_fcmgt0_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_fcmgt0_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_fcmlt0_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_fcmlt0_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_fcmlt0_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_fcmle0_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_fcmle0_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_fcmle0_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_fcmeq0_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_fcmeq0_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_fcmeq0_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_fcmne0_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_fcmne0_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_fcmne0_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_6(sve_fadd_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_6(sve_fadd_s, TCG_CALL_NO_RWG,

10
qemu/target/arm/sve.decode
View file

@ -132,6 +132,7 @@
# One register operand, with governing predicate, vector element size
@rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz
@rd_pg4_pn ........ esz:2 ... ... .. pg:4 . rn:4 rd:5 &rpr_esz
@pd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 . rd:4 &rpr_esz
# One register operand, with governing predicate, no vector element size
@rd_pg_rn_e0 ........ .. ... ... ... pg:3 rn:5 rd:5 &rpr_esz esz=0
@ -758,6 +759,15 @@ FMINV 01100101 .. 000 111 001 ... ..... ..... @rd_pg_rn
FRECPE 01100101 .. 001 110 001100 ..... ..... @rd_rn
FRSQRTE 01100101 .. 001 111 001100 ..... ..... @rd_rn
### SVE FP Compare with Zero Group
FCMGE_ppz0 01100101 .. 0100 00 001 ... ..... 0 .... @pd_pg_rn
FCMGT_ppz0 01100101 .. 0100 00 001 ... ..... 1 .... @pd_pg_rn
FCMLT_ppz0 01100101 .. 0100 01 001 ... ..... 0 .... @pd_pg_rn
FCMLE_ppz0 01100101 .. 0100 01 001 ... ..... 1 .... @pd_pg_rn
FCMEQ_ppz0 01100101 .. 0100 10 001 ... ..... 0 .... @pd_pg_rn
FCMNE_ppz0 01100101 .. 0100 11 001 ... ..... 0 .... @pd_pg_rn
### SVE FP Accumulating Reduction Group
# SVE floating-point serial reduction (predicated)

43
qemu/target/arm/sve_helper.c
View file

@ -3048,6 +3048,8 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, \
#define DO_FCMGE(TYPE, X, Y, ST) TYPE##_compare(Y, X, ST) <= 0
#define DO_FCMGT(TYPE, X, Y, ST) TYPE##_compare(Y, X, ST) < 0
#define DO_FCMLE(TYPE, X, Y, ST) TYPE##_compare(X, Y, ST) <= 0
#define DO_FCMLT(TYPE, X, Y, ST) TYPE##_compare(X, Y, ST) < 0
#define DO_FCMEQ(TYPE, X, Y, ST) TYPE##_compare_quiet(X, Y, ST) == 0
#define DO_FCMNE(TYPE, X, Y, ST) TYPE##_compare_quiet(X, Y, ST) != 0
#define DO_FCMUO(TYPE, X, Y, ST) \
@ -3071,6 +3073,47 @@ DO_FPCMP_PPZZ_ALL(sve_facgt, DO_FACGT)
#undef DO_FPCMP_PPZZ_H
#undef DO_FPCMP_PPZZ
/* One operand floating-point comparison against zero, controlled
* by a predicate.
*/
#define DO_FPCMP_PPZ0(NAME, TYPE, H, OP) \
void HELPER(NAME)(void *vd, void *vn, void *vg, \
void *status, uint32_t desc) \
{ \
intptr_t i = simd_oprsz(desc), j = (i - 1) >> 6; \
uint64_t *d = vd, *g = vg; \
do { \
uint64_t out = 0, pg = g[j]; \
do { \
i -= sizeof(TYPE), out <<= sizeof(TYPE); \
if ((pg >> (i & 63)) & 1) { \
TYPE nn = *(TYPE *)(vn + H(i)); \
out |= OP(TYPE, nn, 0, status); \
} \
} while (i & 63); \
d[j--] = out; \
} while (i > 0); \
}
#define DO_FPCMP_PPZ0_H(NAME, OP) \
DO_FPCMP_PPZ0(NAME##_h, float16, H1_2, OP)
#define DO_FPCMP_PPZ0_S(NAME, OP) \
DO_FPCMP_PPZ0(NAME##_s, float32, H1_4, OP)
#define DO_FPCMP_PPZ0_D(NAME, OP) \
DO_FPCMP_PPZ0(NAME##_d, float64, , OP)
#define DO_FPCMP_PPZ0_ALL(NAME, OP) \
DO_FPCMP_PPZ0_H(NAME, OP) \
DO_FPCMP_PPZ0_S(NAME, OP) \
DO_FPCMP_PPZ0_D(NAME, OP)
DO_FPCMP_PPZ0_ALL(sve_fcmge0, DO_FCMGE)
DO_FPCMP_PPZ0_ALL(sve_fcmgt0, DO_FCMGT)
DO_FPCMP_PPZ0_ALL(sve_fcmle0, DO_FCMLE)
DO_FPCMP_PPZ0_ALL(sve_fcmlt0, DO_FCMLT)
DO_FPCMP_PPZ0_ALL(sve_fcmeq0, DO_FCMEQ)
DO_FPCMP_PPZ0_ALL(sve_fcmne0, DO_FCMNE)
/*
* Load contiguous data, protected by a governing predicate.
*/

44
qemu/target/arm/translate-sve.c
View file

@ -3701,6 +3701,50 @@ static bool trans_FRSQRTE(DisasContext *s, arg_rr_esz *a, uint32_t insn)
return true;
}
/*
*** SVE Floating Point Compare with Zero Group
*/
static void do_ppz_fp(DisasContext *s, arg_rpr_esz *a,
gen_helper_gvec_3_ptr *fn)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
unsigned vsz = vec_full_reg_size(s);
TCGv_ptr status = get_fpstatus_ptr(tcg_ctx, a->esz == MO_16);
tcg_gen_gvec_3_ptr(tcg_ctx, pred_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
pred_full_reg_offset(s, a->pg),
status, vsz, vsz, 0, fn);
tcg_temp_free_ptr(tcg_ctx, status);
}
#define DO_PPZ(NAME, name) \
static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a, uint32_t insn) \
{ \
static gen_helper_gvec_3_ptr * const fns[3] = { \
gen_helper_sve_##name##_h, \
gen_helper_sve_##name##_s, \
gen_helper_sve_##name##_d, \
}; \
if (a->esz == 0) { \
return false; \
} \
if (sve_access_check(s)) { \
do_ppz_fp(s, a, fns[a->esz - 1]); \
} \
return true; \
}
DO_PPZ(FCMGE_ppz0, fcmge0)
DO_PPZ(FCMGT_ppz0, fcmgt0)
DO_PPZ(FCMLE_ppz0, fcmle0)
DO_PPZ(FCMLT_ppz0, fcmlt0)
DO_PPZ(FCMEQ_ppz0, fcmeq0)
DO_PPZ(FCMNE_ppz0, fcmne0)
#undef DO_PPZ
/*
*** SVE Floating Point Accumulating Reduction Group
*/