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target-mips: microMIPS32 R6 POOL32A{XF} instructions

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Add new microMIPS32 Release 6 pool32a/pool32axf instructions.

Backports commit e03320958305a68f2bc6a32c87d7ed48303438f9 from qemu
This commit is contained in:
Yongbok Kim 2018-02-13 22:08:06 -05:00 committed by Lioncash
parent 697b234864
commit f816d6c637
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 72 additions and 10 deletions
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78
qemu/target-mips/translate.c
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@ -13438,6 +13438,10 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
break;
case 0x2c:
switch (minor) {
case BITSWAP:
check_insn(ctx, ISA_MIPS32R6);
gen_bitswap(ctx, OPC_BITSWAP, rs, rt);
break;
case SEB:
gen_bshfl(ctx, OPC_SEB, rs, rt);
break;
@ -13635,7 +13639,11 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
break;
case SDBBP:
check_insn(ctx, ISA_MIPS32);
if (ctx->hflags & MIPS_HFLAG_SBRI) {
generate_exception(ctx, EXCP_RI);
} else {
generate_exception(ctx, EXCP_DBp);
}
break;
default:
goto pool32axf_invalid;
@ -13994,6 +14002,14 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
do_shifti:
gen_shift_imm(ctx, mips32_op, rt, rs, rd);
break;
case SELEQZ:
check_insn(ctx, ISA_MIPS32R6);
gen_cond_move(ctx, OPC_SELEQZ, rd, rs, rt);
break;
case SELNEZ:
check_insn(ctx, ISA_MIPS32R6);
gen_cond_move(ctx, OPC_SELNEZ, rd, rs, rt);
break;
default:
goto pool32a_invalid;
}
@ -14067,16 +14083,52 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
minor = (ctx->opcode >> 6) & 0xf;
switch (minor) {
/* Conditional moves */
case MOVN:
mips32_op = OPC_MOVN;
goto do_cmov;
case MOVZ:
mips32_op = OPC_MOVZ;
do_cmov:
gen_cond_move(ctx, mips32_op, rd, rs, rt);
case MOVN: /* MUL */
if (ctx->insn_flags & ISA_MIPS32R6) {
/* MUL */
gen_r6_muldiv(ctx, R6_OPC_MUL, rd, rs, rt);
} else {
/* MOVN */
gen_cond_move(ctx, OPC_MOVN, rd, rs, rt);
}
break;
case LWXS:
case MOVZ: /* MUH */
if (ctx->insn_flags & ISA_MIPS32R6) {
/* MUH */
gen_r6_muldiv(ctx, R6_OPC_MUH, rd, rs, rt);
} else {
/* MOVZ */
gen_cond_move(ctx, OPC_MOVZ, rd, rs, rt);
}
break;
case MULU:
check_insn(ctx, ISA_MIPS32R6);
gen_r6_muldiv(ctx, R6_OPC_MULU, rd, rs, rt);
break;
case MUHU:
check_insn(ctx, ISA_MIPS32R6);
gen_r6_muldiv(ctx, R6_OPC_MUHU, rd, rs, rt);
break;
case LWXS: /* DIV */
if (ctx->insn_flags & ISA_MIPS32R6) {
/* DIV */
gen_r6_muldiv(ctx, R6_OPC_DIV, rd, rs, rt);
} else {
/* LWXS */
gen_ldxs(ctx, rs, rt, rd);
}
break;
case MOD:
check_insn(ctx, ISA_MIPS32R6);
gen_r6_muldiv(ctx, R6_OPC_MOD, rd, rs, rt);
break;
case R6_DIVU:
check_insn(ctx, ISA_MIPS32R6);
gen_r6_muldiv(ctx, R6_OPC_DIVU, rd, rs, rt);
break;
case MODU:
check_insn(ctx, ISA_MIPS32R6);
gen_r6_muldiv(ctx, R6_OPC_MODU, rd, rs, rt);
break;
default:
goto pool32a_invalid;
@ -14085,6 +14137,16 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
case INS:
gen_bitops(ctx, OPC_INS, rt, rs, rr, rd);
return;
case LSA:
check_insn(ctx, ISA_MIPS32R6);
gen_lsa(ctx, OPC_LSA, rd, rs, rt,
extract32(ctx->opcode, 9, 2));
break;
case ALIGN:
check_insn(ctx, ISA_MIPS32R6);
gen_align(ctx, OPC_ALIGN, rd, rs, rt,
extract32(ctx->opcode, 9, 2));
break;
case EXT:
gen_bitops(ctx, OPC_EXT, rt, rs, rr, rd);
return;