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aarch64: Add pstate pseudoregister

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This commit is contained in:
MerryMage 2018-01-11 18:26:51 +00:00
parent 73f4573535
commit f90c819a33
2 changed files with 8 additions and 0 deletions
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2
include/unicorn/arm64.h
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@ -290,6 +290,8 @@ typedef enum uc_arm64_reg {
UC_ARM64_REG_TPIDR_EL0, UC_ARM64_REG_TPIDR_EL0,
UC_ARM64_REG_TPIDRRO_EL0, UC_ARM64_REG_TPIDRRO_EL0,
UC_ARM64_REG_TPIDR_EL1, UC_ARM64_REG_TPIDR_EL1,
UC_ARM64_REG_PSTATE, // PSTATE pseudoregister
UC_ARM64_REG_ENDING, // <-- mark the end of the list of registers UC_ARM64_REG_ENDING, // <-- mark the end of the list of registers

6
qemu/target-arm/unicorn_aarch64.c
View file

@ -106,6 +106,9 @@ int arm64_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int co
case UC_ARM64_REG_NZCV: case UC_ARM64_REG_NZCV:
*(int32_t *)value = cpsr_read(&ARM_CPU(uc, mycpu)->env) & CPSR_NZCV; *(int32_t *)value = cpsr_read(&ARM_CPU(uc, mycpu)->env) & CPSR_NZCV;
break; break;
case UC_ARM64_REG_PSTATE:
*(uint32_t *)value = pstate_read(&ARM_CPU(uc, mycpu)->env);
break;
} }
} }
} }
@ -174,6 +177,9 @@ int arm64_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals,
case UC_ARM64_REG_NZCV: case UC_ARM64_REG_NZCV:
cpsr_write(&ARM_CPU(uc, mycpu)->env, *(uint32_t *) value, CPSR_NZCV); cpsr_write(&ARM_CPU(uc, mycpu)->env, *(uint32_t *) value, CPSR_NZCV);
break; break;
case UC_ARM64_REG_PSTATE:
pstate_write(&ARM_CPU(uc, mycpu)->env, *(uint32_t *)value);
break;
} }
} }
} }