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target/riscv: Remove manual decoding from gen_load()
With decodetree we don't need to convert RISC-V opcodes into to MemOps as the old gen_load() did. Backports commit 98898b20e9cca462843c22ad952c216ffd57d654 from qemu
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@ -134,34 +134,45 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
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return gen_branch(ctx, a, TCG_COND_GEU);
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}
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static bool gen_load(DisasContext *ctx, arg_lb *a, TCGMemOp memop)
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGv t0 = tcg_temp_new(tcg_ctx);
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TCGv t1 = tcg_temp_new(tcg_ctx);
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gen_get_gpr(ctx, t0, a->rs1);
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tcg_gen_addi_tl(tcg_ctx, t0, t0, a->imm);
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tcg_gen_qemu_ld_tl(ctx->uc, t1, t0, ctx->mem_idx, memop);
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gen_set_gpr(ctx, a->rd, t1);
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tcg_temp_free(tcg_ctx, t0);
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tcg_temp_free(tcg_ctx, t1);
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return true;
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}
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static bool trans_lb(DisasContext *ctx, arg_lb *a)
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{
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gen_load(ctx, OPC_RISC_LB, a->rd, a->rs1, a->imm);
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return true;
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return gen_load(ctx, a, MO_SB);
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}
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static bool trans_lh(DisasContext *ctx, arg_lh *a)
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{
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gen_load(ctx, OPC_RISC_LH, a->rd, a->rs1, a->imm);
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return true;
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return gen_load(ctx, a, MO_TESW);
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}
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static bool trans_lw(DisasContext *ctx, arg_lw *a)
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{
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gen_load(ctx, OPC_RISC_LW, a->rd, a->rs1, a->imm);
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return true;
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return gen_load(ctx, a, MO_TESL);
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}
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static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
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{
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gen_load(ctx, OPC_RISC_LBU, a->rd, a->rs1, a->imm);
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return true;
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return gen_load(ctx, a, MO_UB);
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}
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static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
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{
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gen_load(ctx, OPC_RISC_LHU, a->rd, a->rs1, a->imm);
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return true;
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return gen_load(ctx, a, MO_TEUW);
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}
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static bool trans_sb(DisasContext *ctx, arg_sb *a)
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@ -185,14 +196,12 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a)
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#ifdef TARGET_RISCV64
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static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
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{
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gen_load(ctx, OPC_RISC_LWU, a->rd, a->rs1, a->imm);
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return true;
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return gen_load(ctx, a, MO_TEUL);
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}
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static bool trans_ld(DisasContext *ctx, arg_ld *a)
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{
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gen_load(ctx, OPC_RISC_LD, a->rd, a->rs1, a->imm);
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return true;
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return gen_load(ctx, a, MO_TEQ);
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}
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static bool trans_sd(DisasContext *ctx, arg_sd *a)
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@ -547,7 +547,8 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
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ctx->base.is_jmp = DISAS_NORETURN;
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}
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static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1,
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#ifdef TARGET_RISCV64
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static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
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target_long imm)
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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@ -567,6 +568,7 @@ static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1,
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tcg_temp_free(tcg_ctx, t0);
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tcg_temp_free(tcg_ctx, t1);
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}
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#endif
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static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
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target_long imm)
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@ -747,7 +749,7 @@ static void decode_RV32_64C0(DisasContext *ctx)
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case 3:
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#if defined(TARGET_RISCV64)
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/* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
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gen_load(ctx, OPC_RISC_LD, rd_rs2, rs1s,
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gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
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GET_C_LD_IMM(ctx->opcode));
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#else
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/* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
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