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target/riscv: Remove manual decoding from gen_load()

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With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_load() did.

Backports commit 98898b20e9cca462843c22ad952c216ffd57d654 from qemu
This commit is contained in:
Bastian Koppelmann 2019-03-19 05:02:24 -04:00 committed by Lioncash
parent 6f89816f5d
commit f91f286ed2
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 27 additions and 16 deletions
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37
qemu/target/riscv/insn_trans/trans_rvi.inc.c
View file

@ -134,34 +134,45 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
return gen_branch(ctx, a, TCG_COND_GEU);
}
static bool gen_load(DisasContext *ctx, arg_lb *a, TCGMemOp memop)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
TCGv t1 = tcg_temp_new(tcg_ctx);
gen_get_gpr(ctx, t0, a->rs1);
tcg_gen_addi_tl(tcg_ctx, t0, t0, a->imm);
tcg_gen_qemu_ld_tl(ctx->uc, t1, t0, ctx->mem_idx, memop);
gen_set_gpr(ctx, a->rd, t1);
tcg_temp_free(tcg_ctx, t0);
tcg_temp_free(tcg_ctx, t1);
return true;
}
static bool trans_lb(DisasContext *ctx, arg_lb *a)
{
gen_load(ctx, OPC_RISC_LB, a->rd, a->rs1, a->imm);
return true;
return gen_load(ctx, a, MO_SB);
}
static bool trans_lh(DisasContext *ctx, arg_lh *a)
{
gen_load(ctx, OPC_RISC_LH, a->rd, a->rs1, a->imm);
return true;
return gen_load(ctx, a, MO_TESW);
}
static bool trans_lw(DisasContext *ctx, arg_lw *a)
{
gen_load(ctx, OPC_RISC_LW, a->rd, a->rs1, a->imm);
return true;
return gen_load(ctx, a, MO_TESL);
}
static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
{
gen_load(ctx, OPC_RISC_LBU, a->rd, a->rs1, a->imm);
return true;
return gen_load(ctx, a, MO_UB);
}
static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
{
gen_load(ctx, OPC_RISC_LHU, a->rd, a->rs1, a->imm);
return true;
return gen_load(ctx, a, MO_TEUW);
}
static bool trans_sb(DisasContext *ctx, arg_sb *a)
@ -185,14 +196,12 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a)
#ifdef TARGET_RISCV64
static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
{
gen_load(ctx, OPC_RISC_LWU, a->rd, a->rs1, a->imm);
return true;
return gen_load(ctx, a, MO_TEUL);
}
static bool trans_ld(DisasContext *ctx, arg_ld *a)
{
gen_load(ctx, OPC_RISC_LD, a->rd, a->rs1, a->imm);
return true;
return gen_load(ctx, a, MO_TEQ);
}
static bool trans_sd(DisasContext *ctx, arg_sd *a)

6
qemu/target/riscv/translate.c
View file

@ -547,7 +547,8 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
ctx->base.is_jmp = DISAS_NORETURN;
}
static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1,
#ifdef TARGET_RISCV64
static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
target_long imm)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
@ -567,6 +568,7 @@ static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1,
tcg_temp_free(tcg_ctx, t0);
tcg_temp_free(tcg_ctx, t1);
}
#endif
static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
target_long imm)
@ -747,7 +749,7 @@ static void decode_RV32_64C0(DisasContext *ctx)
case 3:
#if defined(TARGET_RISCV64)
/* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
gen_load(ctx, OPC_RISC_LD, rd_rs2, rs1s,
gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
GET_C_LD_IMM(ctx->opcode));
#else
/* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/