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nvic: Implement Security Attribution Unit registers
Implement the register interface for the SAU: SAU_CTRL, SAU_TYPE, SAU_RNR, SAU_RBAR and SAU_RLAR. None of the actual behaviour is implemented here; registers just read back as written. When the CPU definition for Cortex-M33 is eventually added, its initfn will set cpu->sau_sregion, in the same way that we currently set cpu->pmsav7_dregion for the M3 and M4. Number of SAU regions is typically a configurable CPU parameter, but this patch doesn't provide a QEMU CPU property for it. We can easily add one when we have a board that requires it. Backports commit 9901c576f6c02d43206e5faaf6e362ab7ea83246 from qemu
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@ -277,6 +277,18 @@ static void arm_cpu_reset(CPUState *s)
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env->pmsav8.mair1[M_REG_S] = 0;
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}
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if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
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if (cpu->sau_sregion > 0) {
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memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion);
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memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion);
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}
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env->sau.rnr = 0;
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/* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
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* the Cortex-M33 does.
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*/
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env->sau.ctrl = 0;
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}
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set_flush_to_zero(1, &env->vfp.standard_fp_status);
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set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
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set_default_nan_mode(1, &env->vfp.standard_fp_status);
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@ -652,6 +664,20 @@ static int arm_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err
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}
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}
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if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
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uint32_t nr = cpu->sau_sregion;
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if (nr > 0xff) {
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error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr);
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return -1;
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}
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if (nr) {
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env->sau.rbar = g_new0(uint32_t, nr);
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env->sau.rlar = g_new0(uint32_t, nr);
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}
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}
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if (arm_feature(env, ARM_FEATURE_EL3)) {
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set_feature(env, ARM_FEATURE_VBAR);
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}
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@ -572,6 +572,14 @@ typedef struct CPUARMState {
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uint32_t mair1[M_REG_NUM_BANKS];
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} pmsav8;
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/* v8M SAU */
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struct {
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uint32_t *rbar;
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uint32_t *rlar;
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uint32_t rnr;
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uint32_t ctrl;
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} sau;
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void *nvic;
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const struct arm_boot_info *boot_info;
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@ -661,6 +669,8 @@ typedef struct ARMCPU {
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bool has_mpu;
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/* PMSAv7 MPU number of supported regions */
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uint32_t pmsav7_dregion;
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/* v8M SAU number of supported regions */
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uint32_t sau_sregion;
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/* PSCI conduit used to invoke PSCI methods
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* 0 - disabled, 1 - smc, 2 - hvc
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